MSI MS 6378 User Guide - Page 49

BIOS Setup SDRAM Cycle Length This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: Auto, 2, 3 (clocks). 2 (clocks) increases the system performance the most while 3 (clocks) provides the most stable performance. Auto allows BIOS to determine the best CAS latency length. DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: Auto, 100, 133 (MHz). Auto allows BIOS to determine the best DRAM clock frequency. Memory Hole In order to improve performance, certain space in memory can be reserved for ISA peripherals. This memory must be mapped into the memory space below 16MB. When this area is reserved, it cannot be cached. Settings: Enabled, Disabled. P2C/C2P Concurrency This field enables or disables the PCI to CPU and CPU to PCI concurrency feature, which allows synchronous data transmission from PCI to CPU and vice versa. Selecting Enabled will increase system performance. Fast R-W Turn Around This is used to control the fast read/write turn around feature for DRAM timing. Settings: Enabled, Disabled. Enabled improves system performance while Disabled provides stability. System BIOS Cacheable System BIOS ROM at F0000h-FFFFFh is always copied to RAM for faster execution. Selecting Enabled allows the contents of F0000h RAM memory segment to be written to and read from cache memory, resulting in better system performance. However, if any program writes to this memory area, a system error may result. Settings: Enabled, Disabled. Frame Buffer Size Frame Buffer is the video memory that stores data for video display (frame). This field is used to determine the memory size for Frame Buffer. Larger frame buffer size increases video performance. Settings: 2M, 4M, 8M. 3-13