MSI PT880 User Guide - Page 52

REF to ACT/REF to REF Trfc

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MS-7043 ATX Mainboard DRAM Timing The value in this field depends on performance parameters of the installed memory chips (DRAM). Do not change the value from the factory setting unless you install new memory that has a different performance rating than the original DRAMs. SDRAM CAS# Latency The field controls the CAS latency, which determines the timing delay before SDRAM starts a read command after receiving it. Setting options: [1.5], [2.0], [2.5], [3.0]. [1.5] (clocks) increases system performance while [3.0] (clocks) provides more stable system performance. SDRAM Bank Interleave This field selects 2-bank or 4-bank interleave for the installed DRAM. Disable the function if 16MB DRAM is installed. Setting options: [Enabled], [Disabled]. Precharge to Active (Trp) This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Setting options: [2T] to [5T]. Active to CMD (Trcd) When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. Setting options: [2T] to [5T]. Active to Precharge (Tras) This setting determines the time RAS takes to read from and write to a memory cell. Setting options: [6T] to [9T]. REF to ACT/REF to REF (Trfc) This setting determines the time RFC takes to read from and write to a memory cell. Setting options: [12T] to [15T]. ACT (0) to ACT (1) (Trrd) This setting controls the "DDR row active to row active delay." [2T] performance is better than [3T]. Setting options: [2T], [3T]. DRAM Command Rate This setting controls the DRAM command rate. Selecting [1T] allows DRAM signal controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes DRAM signal controller run at 2T rate. [1T] is faster than [2T]. Setting options: [1T], [2T]. 3-12 DRAM Bus Selection This setting determines the module type of DRAM Bus. Setting options: [Auto], [Single Channel], [Dual Channel].

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3-12
MS-7043 ATX Mainboard
DRAM Timing
The value in this field depends on performance parameters of the installed
memory chips (DRAM). Do not change the value from the factory setting unless
you install new memory that has a different performance rating than the original
DRAMs.
SDRAM CAS# Latency
The field controls the CAS latency, which determines the timing delay before
SDRAM starts a read command after receiving it. Setting options: [1.5], [2.0],
[2.5], [3.0].
[1.5] (clocks) increases system performance while [3.0] (clocks)
provides more stable system performance.
SDRAM Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed DRAM.
Disable
the function if 16MB DRAM is installed. Setting options: [Enabled], [Disabled].
Precharge to Active (Trp)
This setting controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to accu-
mulate its charge before DRAM refresh, refresh may be incomplete and DRAM
may fail to retain data. This item applies only when synchronous DRAM is
installed in the system. Setting options: [2T]
to
[5T].
Active to CMD (Trcd)
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS
(row address strobe) to CAS (column address strobe). The less the clock
cycles, the faster the DRAM performance. Setting options: [2T] to [5T].
Active to Precharge (Tras)
This setting determines the time RAS takes to read from and write to a
memory cell. Setting options: [6T]
to [9T].
REF to ACT/REF to REF (Trfc)
This setting determines the time RFC takes to read from and write to a memory
cell. Setting options: [12T]
to [15T].
ACT (0) to ACT (1) (Trrd)
This setting controls the “DDR row active to row active delay."
[2T] perfor-
mance is better than [3T]. Setting options: [2T], [3T].
DRAM Command Rate
This setting controls the DRAM command rate. Selecting [1T] allows DRAM
signal controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes
DRAM signal controller run at 2T rate. [1T] is faster than [2T]. Setting options:
[1T], [2T].
DRAM Bus Selection
This setting determines the module type of
DRAM Bus. Setting options: [Auto],
[Single Channel], [Dual Channel].