HP Kayak XU 04xx HP Kayak XU PC Workstation Technical Reference Manual Hardwar - Page 20

2 System Board Chip-Set PL Bus Interface PCI Bus Interface AGP Bus Interface Chip-Set The Intel AGPset is comprised of two chips. The 440LX PAC chip and the PIIX4chip. • The PAC chip is the bridge between four buses: the PL bus, the main memory bus, the PCI bus and the AGP (graphic) bus. • The PIIX4 chip is the bridge between three buses: the PCI bus, the SM bus and the ISA bus. In addition, it contains the IDE controller, USB controller and Power Management logic. The PAC Chip (440LX) The PAC chip, called the Intel 440LX AGPset, is contained in a Ball Grid Array (BGA) package, giving a smaller footprint and higher reliability. The PAC chip monitors each cycle that is initiated on the PL bus by the processor, and forwards them to the main memory, PCI bus or AGP bus. The chip can support one or two Pentium II processors, at up to 66 MHz PL bus clock frequency. The PCI bus interface is PCI 2.1 compliant. The PCI arbiter supports PCI bus arbitration for up to six masters using a rotating priority mechanism. Its hidden arbitration scheme minimizes arbitration overhead. Additional logic on the PC Workstation extends the number of fully supported masters to seven (440LX master not counted). A controller for the AGP (Accelerated Graphics Port) slot is integrated in the 440LX PAC chip. Its characteristics and the AGP Bus are described in detail in "Accelerated Graphics Port (AGP) Controller" on page 23. 12