HP Kayak XU 04xx HP Kayak XU PC Workstation Technical Reference Manual Hardwar - Page 73

Disable onboard Super I/O ports and IRQs, Display prompt Press F2 to enter SETUP

Page 73 highlights

5 Power-On Self-Test and Error Messages Order in Which the Tests are Performed Checkpoint Code POST Routine Description 52h Test keyboard 54h Set key click if enabled 56h Enable keyboard 59h Initialize POST display service 5Ah Display prompt "Press F2 to enter SETUP" 5Bh Disable CPU cache 5Ch Test RAM between 512 and 640 KB 60h Test extended memory 62h Test extended memory address lines 64h Jump to UserPatch1 66h Configure advanced cache registers 67h Initialize Multi Processor APIC 68h Enable external and CPU caches 69h Setup System Management Mode (SMM) area 6Ah Display external L2 cache size 6Ch Display shadow-area message 6Eh Display possible high address for UMB recovery 70h Display error messages 72h Check for configuration errors 74h Test real-time clock 76h Check for keyboard errors 7Ah Test for key lock on 7Ch Set up hardware interrupt vectors 7Eh Initialize coprocessor if present 80h Disable onboard Super I/O ports and IRQs 65

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65
5
Power-On Self-Test and Error Messages
Order in Which the Tests are Performed
52h
Test keyboard
54h
Set key click if enabled
56h
Enable keyboard
59h
Initialize POST display service
5Ah
Display prompt “Press F2 to enter SETUP”
5Bh
Disable CPU cache
5Ch
Test RAM between 512 and 640 KB
60h
Test extended memory
62h
Test extended memory address lines
64h
Jump to UserPatch1
66h
Configure advanced cache registers
67h
Initialize Multi Processor APIC
68h
Enable external and CPU caches
69h
Setup System Management Mode (SMM) area
6Ah
Display external L2 cache size
6Ch
Display shadow-area message
6Eh
Display possible high address for UMB recovery
70h
Display error messages
72h
Check for configuration errors
74h
Test real-time clock
76h
Check for keyboard errors
7Ah
Test for key lock on
7Ch
Set up hardware interrupt vectors
7Eh
Initialize coprocessor if present
80h
Disable onboard Super I/O ports and IRQs
Checkpoint
Code
POST Routine Description