HP Kayak XU 04xx HP Kayak XU PC Workstation Technical Reference Manual Hardwar - Page 21

The PIIX4, PCI/ISA Bridge Chip (82371SB)

Get HP Kayak XU 04xx PDF manuals and user guides View all HP Kayak XU 04xx manuals
Add to My Manuals
Save this manual to your list of manuals

Page 21 highlights

2 System Board Chip-Set Main Memory Controller The main memory controller supports four DIMM slots. Each slot can host a 168-pin unbuffered SDRAM module, running at 66 MHz, for a total of up to 512 MB of dynamic random access memory (ECC SDRAM). (Refer to "Main Memory" on page 19, for more detail on the main memory.) The PIIX4, PCI/ISA Bridge Chip (82371SB) The PIIX4 ("PCI-to-ISA/IDE XCELERATOR") chip is encapsulated in a Ball Grid Array (BGA) package. PCI Bus Interface This part of the chip is responsible for transferring data between the PCI bus and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-PCI bus cycle translation. It supports the Plug-and-Play mechanism. Data buffers are provided, to isolate the PCI and ISA buses. The interface complies with the PCI 2.1 specification. ISA Bus Interface As well as accepting cycles from the PCI bus interface, and translating them for the ISA bus, the ISA bus interface also requests the PCI master bridge to generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface contains a standard ISA bus controller and data buffering logic. It can directly support six ISA slots without external data or address buffering. SMBus Controller The System Management (SM) bus is a two-wire serial bus provided by the PIIX4 controller. It runs at a maximum of 16 kHz. The bus monitors some of the hardware functions of the main board, both during boot-up and run-time. All accesses to the SM bus are handled by the main processor, via the PIIX4 SM bus registers. IDE Controller The PCI master/slave IDE controller, supporting two devices on one channel, is described on page 21. USB Controller The PCI USB controller, supporting two connectors, is described on page 22. It is USB 1.0 compliant. 13

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
13
2
System Board
Chip-Set
Main Memory Controller
The main memory controller supports four DIMM slots. Each slot can host a
168-pin unbuffered SDRAM module, running at 66 MHz, for a total of up to
512 MB of dynamic random access memory (ECC SDRAM). (Refer to
“Main
Memory” on page 19
, for more detail on the main memory.)
The PIIX4, PCI/ISA Bridge Chip (82371SB)
The PIIX4 (“PCI-to-ISA/IDE XCELERATOR”) chip is encapsulated in a Ball
Grid Array (BGA) package.
PCI Bus Interface
This part of the chip is responsible for transferring data between the PCI bus
and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-PCI bus cycle
translation. It supports the Plug-and-Play mechanism. Data buffers are
provided, to isolate the PCI and ISA buses. The interface complies with the
PCI 2.1 specification.
ISA Bus Interface
As well as accepting cycles from the PCI bus interface, and translating them
for the ISA bus, the ISA bus interface also requests the PCI master bridge to
generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface
contains a standard ISA bus controller and data buffering logic. It can
directly support six ISA slots without external data or address buffering.
SMBus Controller
The System Management (SM) bus is a two-wire serial bus provided by the
PIIX4 controller. It runs at a maximum of 16 kHz. The bus monitors some of
the hardware functions of the main board, both during boot-up and run-time.
All accesses to the SM bus are handled by the main processor, via the PIIX4
SM bus registers.
IDE Controller
The PCI master/slave IDE controller, supporting two devices on one
channel, is described on
page 21
.
USB Controller
The PCI USB controller, supporting two connectors, is described on page 22.
It is USB 1.0 compliant.