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Hitachi 7K400 Specifications - Page 56

Host Terminating Write DMA

UPC - 000053412935

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6.8.8 Host Terminating Write DMA Table 40: Ultra DMA cycle timing chart (Host Terminating Write) DMARQ DMACKSTOP tLI tSS tLI tMLI tIORDYZ tACK DDMARDYHSTROBE DD(15:0) tLI tACK tCH tCS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx CRC xxxxxxxxxx Host drives DD Table 41: Ultra DMA cycle timings (Host Terminating Write) tSS tLI tMLI tCS tCH tACK tIORDYZ PARAMETER DESCRIPTION (all values in ns) Time from HSTROBE edge to assertion of STOP Limited interlock time Interlock time with minimum CRC word setup time at device CRC word hold time at device Hold time for DMACK- Maximum time before releasing IORDY MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 50 - 50 - 50 - 50 - 50 - 50 - 0 150 0 150 0 150 0 100 0 100 0 75 20 - 20 - 20 - 20 - 20 - 20 - 15 - 10 - 7 - 7 - 5 - 5 - 5-5-5-5-5-5- 20 - 20 - 20 - 20 - 20 - 20 - - 20 - 20 - 20 - 20 - 20 - 20 Deskstar 7K400 Hard Disk Drive Specification 42

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	26
4.3 World Wide Name Assignment	26
4.4 Drive organization	26
4.4.1 Drive format	26
4.4.2 Cylinder allocation	27
4.5 Performance characteristics	28
4.5.1 Command overhead	28
4.5.2 Mechanical positioning	29
4.5.3 Drive ready time	30
4.5.4 Data transfer speed	31
4.5.5 Throughput	32
4.5.6 Operating modes	33
5.0 Defect flagging strategy	35
6.0 Specification	37
6.1 Electrical Interface	37
6.1.1 Connector location	37
6.1.2 DC Power connector	38
6.1.3 AT signal connector	38
6.2 Signal definitions (PATA model)	39
6.3 Signal descriptions	40
6.4 Interface logic signal levels (PATA model)	43
6.4.1 Signal definition (SATA model)	43
6.4.2 Out of band signaling (SATA model)	44
6.5 Signal timings (PATA model)	45
6.5.1 Reset timings	45
6.6 PIO timings	46
6.6.1 Write DRQ interval time	46
6.6.2 Read DRQ interval time	47
6.7 Multi word DMA timings	48
6.8 Ultra DMA timings	49
6.8.1 Initiating Read DMA	49
6.8.2 Host Pausing Read DMA	50
6.8.3 Host Terminating Read DMA	51
6.8.4 Device Terminating Read DMA	52
6.8.5 Initiating Write DMA	53
6.8.6 Device Pausing Write DMA	54
6.8.7 Device Terminating Write DMA	55
6.8.8 Host Terminating Write DMA	56
6.9 Addressing of registers	57
6.9.1 Cabling	57
7.0 Jumper Settings	59
7.1 Connector location	59
7.1.1 Jumper pin identification	59
7.1.2 Jumper pin assignment	60
7.1.3 Jumper positions	60
7.2 Environment	64
7.2.1 Temperature and humidity	64
7.2.2 Corrosion test	65
7.3 DC power requirements	65
7.3.1 Input voltage	65
7.3.2 Power supply current (typical)	65
7.3.3 Power supply generated ripple at drive power connector	66
7.4 Reliability	67
7.4.1 Data integrity	67
7.4.2 Cable noise interference	67
7.4.3 Start/stop cycles	67
7.4.4 Preventive maintenance	67
7.4.5 Data reliability	67
7.4.6 Required power-off sequence	67
7.5 Mechanical specifications	68
7.5.1 Physical dimensions and weight	68
7.5.2 Mounting hole locations	69
7.5.3 Connector locations	70
7.5.4 Drive mounting	71
7.5.5 Heads unload and actuator lock	71
7.6 Vibration and shock	72
7.6.1 Operating vibration	72
7.6.2 Nonoperating vibration	72
7.6.3 Operating shock	73
7.6.4 Nonoperating shock	73
7.6.5 Nonoperating rotational shock	74
7.7 Acoustics	75
7.8 Identification labels	75
7.9 Safety	76
7.9.1 UL and CSA standard conformity	76
7.9.2 German safety mark	76
7.9.3 Flammability	76
7.9.4 Safe handling	76
7.9.5 Environment	76
7.9.6 Secondary circuit protection	76
7.10 Electromagnetic compatibility	77
7.10.1 CE mark	77
7.10.2 C-TICK mark	77
7.10.3 BSMI mark	77
7.11 Packaging	77
8.0 General	79
8.1 Introduction	79
8.2 Terminology	79
8.3 Deviations from standard	79
9.0 Registers	81
9.1 Register set	81
9.2 Alternate Status Register	82
9.3 Command Register	82
9.4 Cylinder High Register	82
9.5 Cylinder Low Register	82
9.6 Data Register	83
9.7 Device Control Register	83
9.8 Drive Address Register	84
9.9 Device/Head Register	84
9.10 Error Register	85
9.11 Features Register	85
9.12 Sector Count Register	85
9.13 Sector Number Register	86
9.14 Status Register	86
10.0 General operation	89
10.1 Reset response	89
10.2 Register initialization	90
10.3 Diagnostic and Reset considerations	91
10.4 Sector Addressing Mode	92
10.4.1 Logical CHS addressing mode	92
10.4.2 LBA addressing mode	92
10.5 Overlapped and queued feature	92
10.6 Power management features	94
10.6.1 Power mode	94
10.6.2 Power management commands	94
10.6.3 Standby timer	94
10.6.4 Interface capability for power modes	95
10.7 S.M.A.R.T. Function	96
10.7.1 Attributes	96
10.7.2 Attribute values	96
10.7.3 Attribute thresholds	96
10.7.4 Threshold exceeded condition	96
10.7.5 S.M.A.R.T. commands	96
10.7.6 Off-line read scanning	96
10.7.7 Error log	97
10.7.8 Self-test	97
10.8 Security Mode Feature Set	98
10.8.1 Security mode	98
10.8.2 Security level	98
10.8.3 Passwords	99
10.8.4 Operation example	99
10.8.5 Command table	102
10.9 Host Protected Area Feature	103
10.9.1 Example for operation (In LBA Mode)	103
10.9.2 Security extensions	104
10.10 Seek overlap	105
10.11 Write cache function	106
10.12 Reassign function	107
10.12.1 Auto Reassign function	107
10.13 Power-Up in Standby feature set	108
10.14 Advanced Power Management feature set (APM)	109
10.15 Automatic Acoustic Management feature set (AAM)	110
10.16 Address Offset Feature	111
10.16.1 Enable/Disable Address Offset Mode	112
10.16.2 Identify Device Data	112
10.16.3 Exceptions in Address Offset Mode	112
10.17 48-bit Address Feature Set	113
10.18 Streaming Feature Set	113
10.18.1 Streaming commands	114
10.18.2 Urgent bit	114
10.18.3 Flush to Disk bit	114
10.18.4 Not Sequential bit	114
10.18.5 Read Continuous bit	115
10.18.6 Write Continuous bit	115
10.18.7 Handle Streaming Error bit	115
10.18.8 Streaming Logs	115
11.0 Command protocol	117
11.1 PIO Data In commands	117
11.2 PIO Data Out Commands	118
11.3 Non-data commands	119
11.4 DMA commands	121
11.5 DMA queued commands	122
12.0 Command descriptions	123
12.1 Check Power Mode (E5h/98h)	127
12.2 Configure Stream (51h)	128
12.3 Device Configuration Overlay (B1h)	130
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h)	130
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (Subcommand C1h)	130
12.3.3 DEVICE CONFIGURATION IDENTIFY (Subcommand C2h)	131
12.3.4 DEVICE CONFIGURATION SET (Subcommand C3h)	131
12.4 Download Microcode (92h)	134
12.5 Execute Device Diagnostic (90h)	135
12.6 Flush Cache (E7h)	136
12.7 Flush Cache Ext (EAh)	137
12.8 Format Track (50h)	138
12.9 Format Unit (F7h)	139
12.10 Identify Device (ECh)	140
12.11 Idle (E3h/97h)	151
12.12 Idle Immediate (E1h/95h)	152
12.13 Initialize Device Parameters (91h)	153
12.14 NOP (00h)	154
12.15 Read Buffer (E4h)	155
12.16 Read DMA (C8h/C9h)	156
12.17 Read DMA Ext (25h)	158
12.18 Read DMA Queued (C7h)	160
12.19 Read DMA Queued Ext (26h)	162
12.20 Read Log Ext (2Fh)	164
12.20.1 General Purpose Log Directory	166
12.20.2 Extended Comprehensive SMART Error Log	167
12.20.3 Extended Self-test log sector	169
12.20.4 Read Stream Error log	170
12.20.5 Write Stream Error log	171
12.20.6 Streaming Performance log	172
12.21 Read Long (22h/23h)	174
12.22 Read Multiple (C4h)	176
12.23 Read Multiple Ext (29h)	178
12.24 Read Native Max ADDRESS (F8h)	180
12.25 Read Native Max Address Ext (27h)	181
12.26 Read Sectors (20h/21h)	182
12.27 Read Sector(s) Ext (24h)	184
12.28 Read Stream DMA (2Ah)	186
12.29 Read Stream PIO (2Bh)	189
12.30 Read Verify Sectors (40h/41h)	192
12.31 Read Verify Sector(s) (42h)	194
12.32 Recalibrate (1xh)	196
12.33 Security Disable Password (F6h)	197
12.34 Security Disable Password (F3h)	198
12.35 Security Erase Unit (F4h)	199
12.36 Security Freeze Lock (F5h)	201
12.37 Security Set Password (F1h)	202
12.38 Security Unlock (F2h)	204
12.39 Seek (7xh)	205
12.40 Service (A2h )	206
12.41 Set Features (EFh)	207
12.41.1 Set Transfer mode	208
12.41.2 Write Cache	208
12.41.3 Advanced Power Management	208
12.41.4 Automatic Acoustic Management	209
12.41.5 Set Maximum Host Interface Sector Time	210
12.42 Set Max ADDRESS (F9h)	211
12.42.1 Set Max Set Password (Feature=01h)	213
12.42.2 Set Max Lock (Feature=02h)	214
12.42.3 Set Max Unlock (Feature = 03h)	215
12.42.4 Set Max Freeze Lock (Feature = 04h)	216
12.43 Set Max Address Ext (37h)	217
12.44 Set Multiple (C6h)	219
12.45 Sleep (E6h/99h)	220
12.46 S.M.A.R.T. Function Set (B0h)	221
12.46.1 S.M.A.R.T. Function Subcommands	221
12.46.2 Device Attribute Data Structure	225
12.46.3 Device Attribute Thresholds data structure	228
12.46.4 S.M.A.R.T. Log Directory	230
12.46.5 S.M.A.R.T. summary error log sector	230
12.46.6 Self-test log data structure	232
12.46.7 Selective self-test log data structure	233
12.46.8 Error reporting	234
12.47 Standby (E2h/96h)	235
12.48 Standby Immediate (E0h/94h)	236
12.49 Write Buffer (E8h)	237
12.50 Write DMA (CAh/CBh)	238
12.51 Write DMA Ext (35h)	240
12.52 Write DMA Queued (CCh)	242
12.53 Write DMA Queued Ext (36h)	244
12.54 Write Log Ext (3Fh)	246
12.55 Write Long (32h/33h)	247
12.56 Write Multiple (C5h)	249
12.57 Write Multiple Ext (39h)	251
12.58 Write Sectors (30h/31h)	253
12.59 Write Sector(s) (34h)	255
12.60 Write Stream DMA (3Ah)	257
12.61 Write Stream PIO (3Bh)	260