Home » Intel Manuals » Desktops » Intel SC5300BD2 » Manual Viewer

Intel SC5300BD2 Product Specification - Page 48

SMBus Monitoring Interface

UPC - 735858171755

Add to My Manuals
Save this manual to your list of manuals

Page 48 highlights

Intel® Server Chassis SC5300 5U Kit TPS Chassis Power Subsystem 3.3.5.1 PSON# Input and Output Signals The PSON# signal is required to remotely turn on/off the power supply. 3.3.5.2 PSKILL The purpose of the PSKill pin is to allow for hot swapping of the power supply. The mating pin of this signal on the power distribution board input connector should be tied to ground, and its resistance shall be less than 5 ohms. 3.3.5.3 PWOK (Power OK) Input and Output Signals PWOK is a Power Good, 5V TTL compatible, coming from the power supply, active HI logic signal, which will be pulled HIGH by the power supply to indicate that its +12V output is within its regulation limits. When its +12V output voltage falls below regulation limits or when AC power has been removed for a time sufficiently long so that power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. 3.3.5.4 lert# Output Signal This signal indicates that the power supply is experiencing a problem that the user should investigate. This signal from each supply is OR-ed on the power distribution board, and then becomes one PSALERT# output signal to the system. See the power supply specification for signal description details. 3.4 SMBus Monitoring Interface The 600-W and 730-W power supplies are compatible with both SMBus 2.0 'high power' and I2C Vdd based power and drive. This bus operates at 3.3V. The SMBus pull-ups are located on the server board. The SMBus provides power monitoring, failure conditions, warning conditions, and FRU data. Two pins have been reserved on the connector to provide this information. One pin is the Serial Clock (PSM Clock). The second pin is used for Serial Data (PSM Data). Both pins are bidirectional and are used to form a serial bus. There are two usage models depending on the system. The system shall control the usage model by setting the Usage Mode bit. Default Mode: In this mode, the LEDs and registers must automatically clear when a warning event has occurred, because there is no software, BIOS, or other agent that will access the power supply via the SMBus to do any clearing. Intelligent Mode: A system management controller or BIOS agent exists that can read and clear status. In this mode, the LEDs and registers should latch when a warning event occurs so that the system and user can read their status before it changes during transient events. There should also be a mechanism to allow the system management or BIOS to 'force' the LED states in order to identify which power supply should be replaced. Critical events will cause the power supply to shutdown and latch the LED and SMBAlert signal no matter what mode the power supply is in; "default" or Intelligent." Revision 1.31 47

Section	Page
Introduction	13
1.1 Intel® Server Chassis SC5300 Design Features	13
1.2 Intel® Server Chassis SC5300BASE Summary	15
1.3 Intel® Server Chassis SC5300BRP Summary	16
1.4 Intel® Server Chassis SC5300LX Summary	16
2. Chassis Features	18
2.1 Chassis Dimensions and Weight	18
System Colors	18
2.2.1 Pedestal and Rack Mount Features	18
2.3 Security	19
2.4 I/O Panel	19
2.5 Standard and Optional Hot Swap Drive Bays	20
2.6 5.25-inch Half-height Peripheral Bays	20
2.7 Chassis Views	21
3. Chassis Power Subsystem	23
3.1 600-W Power Supply	23
3.1.1 Mechanical Outline	23
3.1.2 Output Wire Harness	24
3.1.2.1 Baseboard power connector (P1)	27
3.1.2.2 Processor Power Connector (P2)	27
3.1.2.3 Power Signal Connector (P13)	28
3.1.2.4 Peripheral Power Connectors (P3, P4, and P6, P8 – P11)	28
3.1.2.5 Floppy Power Connector (P6)	29
3.1.2.6 PCI Express Connector (P15)	29
3.1.3 600-W Power Supply Airflow and Temperature Rise	29
3.1.4 AC Specifications	29
3.1.4.1 AC Inlet Connector	30
3.1.4.2 AC Input Voltage Specification	30
3.1.4.3 Efficiency	30
3.1.4.4 AC Line Dropout / Holdup	30
3.1.4.5 AC Line Fuse	30
3.1.5 600-W DC Output Specifications	31
3.1.5.1 Grounding	31
3.1.5.2 Output Voltage and Currents	31
3.1.5.3 Voltage Regulation	32
3.1.5.4 Standby Operation	32
3.1.6 600-W Protection Circuits	32
3.1.6.1 Over Voltage Protection	33
3.1.6.2 Over Temperature Protection	33
3.1.7 600-W Power Supply Control and Indicator Functions	33
3.1.7.1 PSON# Input Signal	33
3.1.7.2 PWOK (Power OK) Output Signal	33
3.1.8 Mean Time Between Failures (MTBF)	33
3.2 730-W Power Supply	33
3.2.1 730W Power Supply Mechanical Outline	34
3.2.2 Output Wire Harness	35
3.2.3 Airflow Requirements and Temperature Rise	35
3.2.4 AC Specifications	35
3.2.4.1 AC Input Voltage Specification	35
3.2.4.2 Efficiency	35
3.2.4.3 AC Line Fuse	36
3.2.5 730-W DC Specifications	36
3.2.5.1 Output Module Edge Connector	36
3.2.5.2 Output Power / Currents	37
3.2.5.3 Standby Outputs	37
3.2.5.4 Stand By Operation	38
3.2.5.5 Voltage Regulation	38
3.2.6 730-W Protection Circuits	38
3.2.6.1 Over Current Protection	38
3.2.6.2 Over Voltage Protection and Over Temperature	38
3.2.7 730-W Power Supply Control and Indicator Functions	39
3.2.7.1 PSON# Input Signal	39
3.2.7.2 PWOK Output Signal	39
3.2.7.3 PSKILL Signal Requirements	39
3.2.8 730-W Mean Time Between Failure (MTBF)	39
3.2.9 Redundant (1+1) Hot Swap Mode	39
3.3 730-W Power Distribution Board	39
3.3.1 Power Distribution Mechanical Overview	40
3.3.2 Temperature Operational Limits	42
3.3.3 Electrical Specification	42
3.3.3.1 Input Connectors	42
3.3.3.2 Baseboard Power Connector (P1)	43
3.3.3.3 Processor Power Connector (P2)	44
3.3.3.4 Peripheral Power Connectors (P3 - P5, P7 - P12)	44
3.3.3.5 Floppy Power Connector (P6)	44
3.3.3.6 Power Signal Connector P13	45
3.3.3.7 12V Output Load Requirements	45
3.3.3.8 DC/DC Converters Loading	46
3.3.3.9 Voltage Regulation	46
3.3.3.10 Fan-less Operation in Stand-by Mode	47
3.3.4 Protection Circuits	47
3.3.4.1 Over Current Protection (OCP) / 240VA Current Limit	47
3.3.4.2 Over Voltage Protection (OVP)	47
3.3.5 Control and Indicator Functions	47
3.3.5.1 PSON# Input and Output Signals	48
3.3.5.2 PSKILL	48
3.3.5.3 PWOK (Power OK) Input and Output Signals	48
3.3.5.4 lert# Output Signal	48
3.4 SMBus Monitoring Interface	48
3.4.1 Mean Time Between Failures (MTBF)	49
4. System Cooling	50
4.1 Fan Configuration	50
4.1.1 Processor Passive Heat Sink Cooling Solution	50
4.1.2 Base Cooling Solution	51
4.1.2 Redundant Cooling Solution	51
4.2 Fan Control	53
4.3 FAN Header Connector Descriptions	53
5. Hard Disk Drive Bays	54
5.1 Server Chassis SC5300 4HDD and 6HDD SCSI HSBP Overview	54
5.1.1 SCSI Enclosure Management Controller	54
5.1.2 SCSI Interface	55
5.1.2.1 I2C Serial Bus Interface	55
5.1.2.2 Temperature Sensor	55
5.1.2.3 Serial EEPROM	55
5.1.3 External Memory Device	55
5.1.4 Hot Swap Power Controller	55
5.1.5 SCSI Drive Connectors	55
5.1.6 Power Connectors	56
5.1.7 SCA2 SCSI Connector	56
5.1.8 68-Pin SCSI Connector	57
5.1.9 IPMB (I2C) Header	59
5.1.10 Power Budget	59
5.1.11 Hard Drive Activity and Fault LED	59
5.1.12 SCSI Backplane Status LEDs.	60
5.1.13 SCSI Hot Swap Drive Bay Upgrade Kits	62
5.2 SATA/SAS Hot Swap Backplane	62
5.2.1 Enclosure Management Controller	64
5.2.2 SATA/SAS Interface	64
5.2.3 I2C Serial Bus Interface	64
5.2.3.1 I2C Bus Address and Loading	65
5.2.3.2 Temperature Sensor	66
5.2.3.3 Serial EEPROM	66
5.2.4 General Purpose Input/Output (GPIO)	66
5.2.5 External Memory Device	68
5.2.6 LEDs	68
5.2.7 SATA/SAS Drive Connectors	68
5.2.8 Power Connectors	69
5.2.9 Clock Generation and Distribution	69
5.2.10 7-Pin SATA/SAS Connector – Drive0-Drive5	70
5.2.11 IPMB Header - IPMB	70
5.2.12 SATA/SAS Host I2C Header - I2C_1	71
5.2.13 Power Budget	71
5.2.14 Board Layout	71
5.2.15 Connector Specifications	72
5.2.16 SATA/SAS Hot Swap Drive Cage Upgrade Kit	73
6. Front Panel	74
6.1 Front Panel Board Layout	74
6.1.1 Front Panel Connectors	74
6.1.2 Front panel JP2 Header (17x2) Pin-out.	75
6.1.3 I2C Connectors at J1 and J2 (Not Installed) Pin-out	76
6.1.4 Front Panel Controls and Indicators	76
6.2 Chassis Interconnect	79
6.3 Chassis Internal Cables	80
6.3.1 Front Panel Cable	80
6.3.2 USB Cable and Connectors	81
6.3.3 Hot Swap Fan Cables and Connectors	81
6.3.4 SCSI Cable	83
6.3.5 Serial Cable	84
6.3.6 SATA Cable	84
6.3.7 IPMB cable for 6-Drive Bays (4-pin)	85
6.3.8 I2C Cable for 6-Drive Bays (3-pin)	85
7. System-Compatible Server Boards	86
8. Upgrade Accessories	87
8.1 AXX6SCSIDB and AXX4SCSIDB Hot Swap SCSI Drive Bays	87
8.2 SATA/SAS Hot Swap Drive Bay Upgrade Accessory AXX6SASDB	87
8.3 External SCSI Adapter Cable AXXEXTSCSICBL	87
8.4 Rack Conversion Kit ARIGRACK	87
9. Reliability, Serviceability, and Availability	88
9.1 MTBF	88
9.2 Serviceability	88
10. Environmental Limits	90
10.1 System Office Environment	90
10.2 System Environmental Testing	90
11. Product Regulatory Compliance	91
11.1 Product Safety Compliance	91
11.2 Product EMC Compliance	91
11.3 Product Regulatory Compliance Markings	91
11.4 Electromagnetic Compatibility Notices	92
11.4.1 USA	92
11.4.2 FCC Verification Statement	93
11.4.3 ICES-003 (Canada)	93
11.4.4 Europe (CE Declaration of Conformity)	93
11.4.5 Japan EMC Compatibility	93

Match case Limit results 1 per page

Intel® Server Chassis SC5300 5U Kit TPS

Chassis Power Subsystem

Revision 1.31

3.3.5.1

PSON#

Input and Output Signals

The PSON# signal is required to remotely turn on/off the power supply.

3.3.5.2

PSKILL

The purpose of the PSKill pin is to allow for hot swapping of the power supply. The mating pin of

this signal on the power distribution board input connector should be tied to ground, and its

resistance shall be less than 5 ohms.

3.3.5.3

PWOK (Power OK) Input and Output Signals

PWOK is a Power Good, 5V TTL compatible, coming from the power supply, active HI logic

signal, which will be pulled HIGH by the power supply to indicate that its +12V output is within

its regulation limits. When its +12V output voltage falls below regulation limits or when AC

power has been removed for a time sufficiently long so that power supply operation is no longer

guaranteed, PWOK will be de-asserted to a LOW state.

3.3.5.4

lert# Output Signal

This signal indicates that the power supply is experiencing a problem that the user should

investigate. This signal from each supply is OR-ed on the power distribution board, and then

becomes one PSALERT# output signal to the system. See the power supply specification for

signal description details.

3.4

SMBus Monitoring Interface

The 600-W and 730-W power supplies are compatible with both SMBus 2.0 ‘high power’ and

C Vdd based power and drive. This bus operates at 3.3V. The SMBus pull-ups are located on

the server board.

The SMBus provides power monitoring, failure conditions, warning conditions, and FRU data.

Two pins have been reserved on the connector to provide this information. One pin is the Serial

Clock (PSM Clock). The second pin is used for Serial Data (PSM Data). Both pins are bi-

directional and are used to form a serial bus.

There are two usage models depending on the system. The system shall control the usage

model by setting the Usage Mode bit.

Default Mode:

In this mode, the LEDs and registers must automatically clear when a warning

event has occurred, because there is no software, BIOS, or other agent that will access the

power supply via the SMBus to do any clearing.

Intelligent Mode:

A system management controller or BIOS agent exists that can read and clear

status. In this mode, the LEDs and registers should latch when a warning event occurs so that

the system and user can read their status before it changes during transient events. There

should also be a mechanism to allow the system management or BIOS to ‘force’ the LED states

in order to identify which power supply should be replaced.

Critical events will cause the power supply to shutdown and latch the LED and SMBAlert signal

no matter what mode the power supply is in; “default” or Intelligent.”