Intel SE7525RP2 Product Specification - Page 43

Jumperless Processor Speed Settings, 2.1.7, Microcode, 2.1.8, Processor Cache, 2.1.9, Hyper-

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.2.1.6 Jumperless Processor Speed Settings The Intel® Xeon™ processor does not use jumpers or switches to set the processor frequency. The BIOS reads the highest ratio register from all processors in the system. If all processors are the same speed, the Actual Ratio register is programmed with the value read from the High Ratio register. If all processors do not match, the highest common value between High and Low Ratio is determined and programmed to all processors. If no value works for all installed processors, all processors not capable of speeds supported by the BSP are disabled and an error is displayed. 6.2.1.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intelsupplied data block (i.e., microcode update). The BIOS is responsible for storing the update in non-volatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available. The BIOS supports variable size microcode updates and verifies the signature prior to storing the update in the flash. The system BIOS supports the real mode INT15, D042h interface for updating the microcode updates in the flash. 6.2.1.8 Processor Cache The BIOS enables all levels of processor cache as early as possible during. There are no user options to modify the cache configuration, size or policies. All detected cache sizes are reported in the SMBIOS Type 7 structures. 6.2.1.9 Hyper-Threading Technology Intel® XeonTM processors support Hyper-Threading Technology. The BIOS detects processors that support this feature and enables the feature during POST. BIOS Setup provides an option to selectively enable or disable this feature. The default behavior is enabled. If enabled, the BIOS creates additional entries in the ACPI MP tables to describe the virtual processors. The SMBIOS Type 4 structure shows only the physical processors installed. It does not describe the virtual processors. Because some operating systems are not able to efficiently utilize the Hyper-Threading Technology, the BIOS does not create entries in the MP tables to describe the virtual processors. 6.2.1.10 Intel SpeedStep® Technology Intel® Xeon™ processors support the Geyserville3 (GV3) feature of the Intel SpeedStep® Technology. This feature changes the processor operating ratio and voltage similar to the Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature. The BIOS implements the GV3 feature in conjunction with the TM2 feature. Revision 1.0 43 Intel order number D24635-001

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
BIOS
Revision 1.0
Intel order number D24635-001
43
6.2.1.6
Jumperless Processor Speed Settings
The Intel® Xeon™ processor does not use jumpers or switches to set the processor frequency.
The BIOS reads the highest ratio register from all processors in the system. If all processors are
the same speed, the Actual Ratio register is programmed with the value read from the High
Ratio register. If all processors do not match, the highest common value between High and Low
Ratio is determined and programmed to all processors. If no value works for all installed
processors, all processors not capable of speeds supported by the BSP are disabled and an
error is displayed.
6.2.1.7
Microcode
IA-32 processors have the capability of correcting specific errata through the loading of an Intel-
supplied data block (i.e., microcode update). The BIOS is responsible for storing the update in
non-volatile memory and loading it into each processor during POST. The BIOS allows a
number of microcode updates to be stored in the flash, limited by the amount of free space
available. The BIOS supports variable size microcode updates and verifies the signature prior to
storing the update in the flash. The system BIOS supports the real mode INT15, D042h
interface for updating the microcode updates in the flash.
6.2.1.8
Processor Cache
The BIOS enables all levels of processor cache as early as possible during. There are no user
options to modify the cache configuration, size or policies. All detected cache sizes are reported
in the SMBIOS Type 7 structures.
6.2.1.9
Hyper-Threading Technology
Intel® Xeon
TM
processors support Hyper-Threading Technology. The BIOS detects processors
that support this feature and enables the feature during POST. BIOS Setup provides an option
to selectively enable or disable this feature. The default behavior is enabled.
If enabled, the BIOS creates additional entries in the ACPI MP tables to describe the virtual
processors. The SMBIOS Type 4 structure shows only the physical processors installed. It does
not describe the virtual processors.
Because some operating systems are not able to efficiently utilize the Hyper-Threading
Technology, the BIOS does not create entries in the MP tables to describe the virtual
processors.
6.2.1.10
Intel SpeedStep® Technology
Intel
®
Xeon™ processors support the Geyserville3 (GV3) feature of the Intel SpeedStep®
Technology. This feature changes the processor operating ratio and voltage similar to the
Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature.
The BIOS implements the GV3 feature in conjunction with the TM2 feature.