Intel SE7525RP2 Product Specification - Page 90

POST Code Checkpoints

Get Intel SE7525RP2 PDF manuals and user guides View all Intel SE7525RP2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 90 highlights

Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.1.2 POST Code Checkpoints The following table describes the type of checkpoints that may occur during the POST portion of the BIOS. Table 50. POST Code Checkpoints Checkpoint 03 04 05 06 08 C0 C1 C2 C5 C6 C7 0A 0B 0C 0E 13 24 30 2A 2C 2E 31 33 37 38 39 3A Description Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. Do a read/write test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. Early CPU Init Start -- Disable Cache - Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate and set up application processors Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and silent logo modules. Early POST initialization of chipset registers. Uncompress and initialize any platform specific BIOS modules. Initialize System Management Interrupt. Initializes different devices through DIM. See Section 9.4.1.5 for information. Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs. Initializes all the output devices. Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module. Initializes the silent boot module. Set the window for displaying text information. Displaying sign-on message, CPU information, setup key message, and any OEM specific information. Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. Initializes DMAC-1 and DMAC-2. Initialize RTC date/time. 90 Revision 1.0 Intel order number D24635-001

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
Error Logging
Revision 1.0
Intel order number D24635-001
90
9.4.1.2
POST Code Checkpoints
The following table describes the type of checkpoints that may occur during the POST portion of
the BIOS.
Table 50. POST Code Checkpoints
Checkpoint
Description
03
Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area.
Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the
Kernel Variable "wCMOSFlags."
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify
CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS
with power-on default values and clear passwords. Initialize status register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible
PICs in the system
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06
Do a read/write test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
08
Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command
byte is being done after Auto detection of KB/MS using AMI KB-5.
C0
Early CPU Init Start -- Disable Cache - Init Local APIC
C1
Set up boot strap processor Information
C2
Set up boot strap processor for POST
C5
Enumerate and set up application processors
C6
Re-enable cache for boot strap processor
C7
Early CPU Init Exit
0A
Initializes the 8042 compatible Key Board Controller.
0B
Detects the presence of PS/2 mouse.
0C
Detects the presence of Keyboard in KBC port.
0E
Testing and initialization of different Input Devices. Update the Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all
available language, BIOS logo, and silent logo modules.
13
Early POST initialization of chipset registers.
24
Uncompress and initialize any platform specific BIOS modules.
30
Initialize System Management Interrupt.
2A
Initializes different devices through DIM. See Section 9.4.1.5 for information.
2C
Initializes different devices. Detects and initializes the video adapter installed in the system that have
optional ROMs.
2E
Initializes all the output devices.
31
Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization.
Initialize language and font modules for ADM. Activate ADM module.
33
Initializes the silent boot module. Set the window for displaying text information.
37
Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38
Initializes different devices through DIM. See DIM Code Checkpoints section of document for more
information.
39
Initializes DMAC-1 and DMAC-2.
3A
Initialize RTC date/time.