Intel SE7525RP2 Product Specification - Page 50

Retry on Uncorrectable Error, 2.2.7.4, Integrated Memory Initialization Engine, 2.2.7.5, - ram

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS An uncorrectable error encountered by the memory scrub engine is a "speculative error." This designation is applied because no system agent has specifically requested the use of the corrupt data, and no real error condition exists in the system until that occurs. It is possible that the error residing in an unmodified page of memory will be dropped on a swap-back to disk. If that happens, the speculative error would simply "vanish" from the system undetected and without adverse consequences. 6.2.2.7.3 Retry on Uncorrectable Error The Intel E7320/ E7525 MCH includes specialized hardware to resubmit a memory read request upon detection of an uncorrectable error. When a demand fetch (as opposed to a scrub) of memory encounters an uncorrectable error as determined by the enabled ECC algorithm, the memory control hardware will cause a (single) full resubmission of the entire cache line request from memory to verify the existence of corrupt data. This feature is expected to reduce or eliminate the reporting of false or transient uncorrectable errors in the DRAM array. Any given read request will only be retried once on behalf of this error detection mechanism. If the uncorrectable error is repeated, it will be logged and escalated as directed by the device configuration. This RASUM feature may be enabled and disabled. 6.2.2.7.4 Integrated Memory Initialization Engine The Intel E7320 / E7525 MCH provides hardware managed ECC auto-initialization of all populated DRAM space under software control. Once internal configuration has been updated to reflect the types and sizes of populated DIMM devices, the MCH will traverse the populated address space initializing all locations with good ECC. This not only speeds up the mandatory memory initialization step, but also frees the processor to pursue other machine initialization and configuration tasks. Additional features have been added to the initialization engine to support high speed population and verification of a programmable memory range with one of four known data patterns (0/F, A/5, 3/C, and 6/9). This function facilitates a limited, very high speed memory test, and provides a BIOS accessible memory zeroing capability for use by the operating system. 6.2.2.7.5 DIMM Sparing Function To provide a more fault tolerant system, the Intel E7320/ E7525 MCH includes specialized hardware to support fail-over to a spare DIMM device in case a primary DIMM in use exceeds a specified threshold of runtime errors. One of the DIMMs installed per channel, greater than or equal in size than the largest primary DIMM, will not be used but is kept in reserve. If a significant failure occurs in a particular DIMM, that DIMM and its corresponding partner in the other channel (if applicable), will, over time, have its data copied to the spare DIMM(s). When all the data has been copied, the reserve DIMM(s) will be put into service and the failing DIMM will be removed from service. Only one sparing cycle is supported. If this feature is not enabled, then all DIMMs will be visible in normal address space. Note: The Server Boards SE7320EP2 and SE7525RP2 do not support the memory sparing for dual-rank DDR2 RAM. DIMM Sparing feature requires that the spare DIMM be at least the size of the largest primary DIMM in use. 50 Revision 1.0 Intel order number D24635-001

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
BIOS
Revision 1.0
Intel order number D24635-001
50
An uncorrectable error encountered by the memory scrub engine is a “speculative error.” This
designation is applied because no system agent has specifically requested the use of the
corrupt data, and no real error condition exists in the system until that occurs. It is possible that
the error residing in an unmodified page of memory will be dropped on a swap-back to disk. If
that happens, the speculative error would simply “vanish” from the system undetected and
without adverse consequences.
6.2.2.7.3
Retry on Uncorrectable Error
The Intel E7320/ E7525 MCH includes specialized hardware to resubmit a memory read request
upon detection of an uncorrectable error. When a demand fetch (as opposed to a scrub) of
memory encounters an uncorrectable error as determined by the enabled ECC algorithm, the
memory control hardware will cause a (single) full resubmission of the entire cache line request
from memory to verify the existence of corrupt data. This feature is expected to reduce or
eliminate the reporting of false or transient uncorrectable errors in the DRAM array.
Any given read request will only be retried once on behalf of this error detection mechanism. If
the uncorrectable error is repeated, it will be logged and escalated as directed by the device
configuration. This RASUM feature may be enabled and disabled.
6.2.2.7.4
Integrated Memory Initialization Engine
The Intel E7320 / E7525 MCH provides hardware managed ECC auto-initialization of all
populated DRAM space under software control. Once internal configuration has been updated
to reflect the types and sizes of populated DIMM devices, the MCH will traverse the populated
address space initializing all locations with good ECC. This not only speeds up the mandatory
memory initialization step, but also frees the processor to pursue other machine initialization
and configuration tasks.
Additional features have been added to the initialization engine to support high speed
population and verification of a programmable memory range with one of four known data
patterns (0/F, A/5, 3/C, and 6/9). This function facilitates a limited, very high speed memory test,
and provides a BIOS accessible memory zeroing capability for use by the operating system.
6.2.2.7.5
DIMM Sparing Function
To provide a more fault tolerant system, the Intel E7320/ E7525 MCH includes specialized
hardware to support fail-over to a spare DIMM device in case a primary DIMM in use exceeds a
specified threshold of runtime errors. One of the DIMMs installed per channel, greater than or
equal in size than the largest primary DIMM, will not be used but is kept in reserve. If a
significant failure occurs in a particular DIMM, that DIMM and its corresponding partner in the
other channel (if applicable), will, over time, have its data copied to the spare DIMM(s). When all
the data has been copied, the reserve DIMM(s) will be put into service and the failing DIMM will
be removed from service. Only one sparing cycle is supported. If this feature is not enabled,
then all DIMMs will be visible in normal address space.
Note:
The Server Boards SE7320EP2 and SE7525RP2 do not support the memory sparing for
dual-rank DDR2 RAM. DIMM Sparing feature requires that the spare DIMM be at least the size
of the largest primary DIMM in use.