Intel SE7525RP2 Product Specification - Page 91

Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS, Error Logging, Revision 1.0,

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Checkpoint 3B 3C 40 50 52 60 75 78 7A 7C 84 85 87 8C 8D 8E 90 A0 A1 A2 A4 A7 A8 A9 AA AB AC B1 00 61-70 Description Test for total memory installed in the system. Also, Check for DEL or keys to limit memory test. Display total memory in the system. Mid POST initialization of chipset registers. Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA...etc. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed. Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Initializes NUM-LOCK status and programs the KBD typematic rate. Initialize Int-13 and prepare for IPL detection. Initializes IPL devices controlled by BIOS and option ROMs. Initializes remaining option ROMs. Generate and write contents of ESCD in NVRam. Log errors encountered during POST. Display errors to the user and gets the user response for error. Execute BIOS setup if needed / requested. Late POST initialization of chipset registers. Build ACPI tables (if ACPI is supported) Program the peripheral parameters. Enable/Disable NMI as selected Late POST initialization of system management interrupt. Check boot password if installed. Clean-up work needed before booting to operating system. Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. Initialize runtime language module. Displays the system configuration screen if enabled. Initialize the CPU's before boot, which includes the programming of the MTRR's. Prepare CPU for operating system boot including final MTRR values. Wait for user input at config display if needed. Uninstall POST INT1Ch vector and INT09h vector. De-initializes the ADM module. Prepare BBS for Int 19 boot. End of POST initialization of chipset registers. Save system context for ACPI. Passes control to OS Loader (typically INT19h). OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next. Revision 1.0 91 Intel order number D24635-001

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Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
Error Logging
Revision 1.0
Intel order number D24635-001
91
Checkpoint
Description
3B
Test for total memory installed in the system. Also, Check for DEL or <Esc> keys to limit memory test.
Display total memory in the system.
3C
Mid POST initialization of chipset registers.
40
Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully
installed in the system and update the BDA, EBDA…etc.
50
Programming the memory hole or any kind of implementation that needs an adjustment in system
RAM size if needed.
52
Updates CMOS memory size from memory found in memory test. Allocates memory for Extended
BIOS Data Area from base memory.
60
Initializes NUM-LOCK status and programs the KBD typematic rate.
75
Initialize Int-13 and prepare for IPL detection.
78
Initializes IPL devices controlled by BIOS and option ROMs.
7A
Initializes remaining option ROMs.
7C
Generate and write contents of ESCD in NVRam.
84
Log errors encountered during POST.
85
Display errors to the user and gets the user response for error.
87
Execute BIOS setup if needed / requested.
8C
Late POST initialization of chipset registers.
8D
Build ACPI tables (if ACPI is supported)
8E
Program the peripheral parameters. Enable/Disable NMI as selected
90
Late POST initialization of system management interrupt.
A0
Check boot password if installed.
A1
Clean-up work needed before booting to operating system.
A2
Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h
segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language
module. Disables the system configuration display if needed.
A4
Initialize runtime language module.
A7
Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which includes
the programming of the MTRR’s.
A8
Prepare CPU for operating system boot including final MTRR values.
A9
Wait for user input at config display if needed.
AA
Uninstall POST INT1Ch vector and INT09h vector. De-initializes the ADM module.
AB
Prepare BBS for Int 19 boot.
AC
End of POST initialization of chipset registers.
B1
Save system context for ACPI.
00
Passes control to OS Loader (typically INT19h).
61-70
OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error
associated with this value may be different from one platform to the next.