LG KU580 Service Manual - Page 69

C. Synthesizer

Page 69 highlights

3. Technical Brief C. Synthesizer The RX and TX RF VCOs are fully integrated and self-calibrated on manufacturing tolerances. They have 16 different frequency ranges that are selected internally depending on the frequency programming. The calibration is done on each low to high logical transition of the SYNON bit in the control register or on each change of the integer divider ratio of the RF fractional N synthesizer. A high-performance RF fractional-N synthesizer PLL is included on-chip which enables the frequency of the RF VCO to be synthesized. The frequency is set through the 3-wire serial programming bus. The PLL is based on Sigma-Delta (∑) fractional-N synthesis that enables the required channel frequency, including Automatic Frequency Control (AFC) from a free running external 26 MHz reference frequency. Very low close-in-phase noise is achieved. This allows widening of the PLL loop bandwidth and shorter settling time. The programmable main dividers are controlled by a second order ∑-modulus controller. They divide the RF VCO signals down to frequencies of 26 MHz (12 Hz step programmability). Their phase is then compared in a digital Phase/Frequency Detector (PFD) to the 26 MHz reference clock signal. The phase error information is fed back to the RF VCO through the charge pump circuit that .sources. into or .sinks. current from the loop filter capacitor, thus changing the VCO frequency such that the loop finally gets phase-locked. WTXMOD_BAND_I R118 0 R119 52 G2 G1 OUT IN 4 G3 1 0 SAFEB1G95KA0F00 3 FL102 L105 NA R120 0 C122 NA C123 NA VRADA_2V75 C126 NA WTX_I_P WTX_I_N WTX_Q_P WTX_Q_N VRADA_2V75 WPA_BIAS WPA_VCC C120 NA FL100 R117 0 SAFEB2G14FA0F00 45 O2 G2 IN O1 G1 1 32 L106 5.6nH C125 NA C124 NA 41 PGND 40 VCCTX 39 RF_DAC2 38 RF_DAC1 37 NC13 36 MIX1_B 35 MIX1_A 34 NC12 33 NC11 32 NC10 31 VCCRX 1 30 GNDTX NC9 2 29 NC1 LNA1_OUT 3 28 NC2 NC8 4 TX_1 5 U104 27 LNA1_IN 26 NC3 NC7 6 25 VCCLOTX NC6 7 24 TXIA VCCLORX 8 TXIB RF3100_OM6195HN NC5 23 9 22 TXQA VDD 10 21 TXQB TST VRADA_2V75 VDIGRAD_1V8 VRADA_2V75 C130 NA C127 5.6p C131 NA R121 0 L107 4.7nH 11 VGACTL 12 DATA 13 CLK 14 EN 15 REFIN 16 NC4 17 RXIA 18 RXIB 19 RXQA 20 RXQB RF_CTRL_DATA RF_CTRL_CLK RF_CTRL_STRB WCLK C133 8.2p R124 200 R127 200 R128 200 R129 200 WRX_Q_N WRX_Q_P WRX_I_N WRX_I_P Figure 3-7-4. WCDMA Transceiver schematic WRX_BAND_I LGE Internal Use Only - 70 - Copyright © 2007 LG Electronics. Inc. All right reserved. Only for training and service purposes

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C. Synthesizer
The RX and TX RF VCOs are fully integrated and self-calibrated on manufacturing tolerances.
They have 16 different frequency ranges that are selected internally depending on the frequency
programming. The calibration is done on each low to high logical transition of the SYNON bit in the
control register or on each change of the integer divider ratio of the RF fractional N synthesizer.
A high-performance RF fractional-N synthesizer PLL is included on-chip which enables the frequency
of the RF VCO to be synthesized. The frequency is set through the 3-wire serial programming bus.
The PLL is based on Sigma-Delta (∑) fractional-N synthesis that enables the required channel
frequency, including Automatic Frequency Control (AFC) from a free running external 26 MHz
reference frequency. Very low close-in-phase noise is achieved. This allows widening of the PLL loop
bandwidth and shorter settling time. The programmable main dividers are controlled by a second order
∑-modulus controller. They divide the RF VCO signals down to frequencies of 26 MHz (12 Hz step
programmability). Their phase is then compared in a digital Phase/Frequency Detector (PFD) to the 26
MHz reference clock signal.
The phase error information is fed back to the RF VCO through the charge pump circuit that .sources.
into or .sinks. current from the loop filter capacitor, thus changing the VCO frequency such that the
loop finally gets phase-locked.
- 70 -
3. Technical Brief
LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc.
All right reserved.
Only for training and service purposes
Figure 3-7-4. WCDMA Transceiver schematic
NA
C130
C124
L106
5.6nH
NA
C131
NA
0
R120
NA
NA
C122
C123
C126
NA
R118
0
L105
NA
NA
C125
FL100
G1
2
G2
5
IN
1
O1
3
O2
4
G1
2
G2
5
G3
3
1
IN
4
OUT
SAFEB2G14FA0F00
FL102
SAFEB1G95KA0F00
21
7
TXIA
TXIB
8
9
TXQA
TXQB
10
TX_1
4
24
VCCLORX
VCCLOTX
6
VCCRX
31
VCCTX
40
VDD
22
11
VGACTL
NC2
5
NC3
NC4
16
23
NC5
NC6
25
26
NC7
28
NC8
30
NC9
41
PGND
15
REFIN
RF_DAC1
38
39
RF_DAC2
RXIA
17
RXIB
18
RXQA
19
20
RXQB
TST
RF3100_OM6195HN
CLK
13
12
DATA
14
EN
GNDTX
1
LNA1_IN
27
LNA1_OUT
29
MIX1_A
35
36
MIX1_B
NC1
2
NC10
32
33
NC11
NC12
34
NC13
37
3
U104
VDIGRAD_1V8
C120
NA
0
R117
VRADA_2V75
VRADA_2V75
VRADA_2V75
VRADA_2V75
R129
200
R128
200
R127
200
0
R119
L107
4.7nH
0
R121
5.6p
C127
C133 8.2p
R124
200
WTXMOD_BAND_I
WRX_Q_N
WRX_Q_P
WRX_I_N
WRX_I_P
WRX_BAND_I
RF_CTRL_CLK
RF_CTRL_DATA
RF_CTRL_STRB
WCLK
WPA_BIAS
WPA_VCC
WTX_I_P
WTX_I_N
WTX_Q_P
WTX_Q_N