Lenovo NetVista Technical information manual for NetVista 6269, 6568, 6569, 65 - Page 17

PCI bus The fully synchronous 32-bit 33 MHz PCI bus originates in the chip set. Features of these PCI buses are: • Integrated arbiter with multitransaction, PCI-arbitration, acceleration hooks • Zero-wait-state, microprocessor-to-PCI write interface for high-performance graphics • Built-in PCI bus arbiter with support for all PCI devices and connectors • Microprocessor-to-PCI memory write posting • Conversion of back-to-back, sequential, microprocessor-to-PCI memory write to PCI burst write • PCI-to-DRAM memory up to 528 megabytes per second (MBps) speed • PCI 2.2 compliant • Delayed transaction • PCI parity checking and generation support IDE bus master interface The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with Extensions standard. The bus master for the IDE interface is integrated into the Intel 815E or 810E chip set, depending on the model. The chip set connects directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and the IDE bus. The 815E chip set is capable of supporting PIO mode 0-4 devices and IDE DMA mode 0-5 devices, and ATA 100 transfers of up to 100 Megabytes per second. The 810E chip set is capable of supporting PIO mode 0-4 devices and IDE DMA mode 0-4 devices, and ATA 66 transfers of up to 66 Megabytes per second. The IDE devices receive their power through a four-position power cable containing +5 v dc, +12 v dc, and ground voltage. When devices are added to the IDE interface, one device is designated as the master (primary) device and another is designated as the slave (secondary) device. These designations are determined by jumpers on each device. Two connectors are provided on the system board for the IDE interface. One connector is designated Primary, and the other connector is designated Secondary. Each connector allows two devices to be attached, allowing up to four devices to be attached to the IDE interface. For information on the connector pin assignments, see "IDE connectors" on page 33. For the IDE interface, no resource assignments are given in the system memory or the direct memory access (DMA) channels. For information on the resource assignments, see Table 36 on page 49. USB interface USB technology is a standard feature of the computer. The A40 and A40p system boards provide the USB interface with two dual channels integrated into the chip set. The A20 system board provides the USB interface with one dual channel integrated into the chip set. A USB-enabled device can attach to a connector, and if that device is a hub, multiple peripheral devices can attach to the hub and be used by the system. The USB connectors use Plug and Play technology for installed devices. The speed of the USB is up to 12 MBps with a maximum of 127 peripheral devices. The USB is compliant with Universal Host Controller Interface Guide 1.0. Chapter 2. System board features 7