Lenovo NetVista Technical information manual for NetVista 6269, 6568, 6569, 65 - Page 57

Table 33. I/O address map Address (hex) Size (bytes) 03E0 - 03E7 8 03E8 - 03EF 8 03F0 - 03F5 6 03F6 1 03F7 (Write) 1 03F7, bit 7 1 bit 03F7, bits 6:0 7 bits 03F8 - 03FF 8 0400 - 047F 128 0480 - 048F 0490 - 0CF7 16 1912 0CF8 - 0CFB 4 0CFC - 0CFF 4 LPTn + 400h 8 OCF9 1 0D00 - FFFF 62207 Description Available COM3 or COM4 Diskette channel 1 Primary IDE channel command port Diskette channel 1 command Diskette disk change channel Primary IDE channel status port COM1 Available DMA channel high page registers Available PCI configuration address register PCI configuration data register ECP port, LPTn base address + hex 400 Turbo and reset control register Available DMA I/O address map The following figure lists resource assignments for the DMA address map. Any addresses that are not shown are reserved. Table 34. DMA I/O address map Address (hex) Description 0000 Channel 0, memory address register 0001 Channel 0, transfer count register 0002 0003 Channel 1, memory address register Channel 1, transfer count register 0004 Channel 2, memory address register 0005 Channel 2, transfer count register 0006 0007 Channel 3, memory address register Channel 3, transfer count register 0008 Channels 0-3, read status/write command register 0009 Channels 0-3, write request register 000A Channels 0-3, write single mas register bits 000B 000C Channels 0-3, mode register (write) Channels 0-3, clear byte pointer (write) 000D Channels 0-3, master clear (write)/temp (read) Bits 00 - 15 00 - 15 00 - 15 00 - 15 00 - 15 00 - 15 00 - 15 00 - 15 00 - 07 00 - 02 00 - 02 00 - 07 A 00 - 07 Byte pointer Yes Yes Yes Yes Yes Yes Yes Yes Appendix B. System address maps 47