Lenovo NetVista Technical information manual for NetVista 6269, 6568, 6569, 65 - Page 37

Chapter 6. System compatibility This chapter discusses some of the hardware, software, and BIOS compatibility issues that must be considered when designing application programs for the computer. Hardware compatibility The functional interfaces are compatible with the following interfaces: • Intel 8259 interrupt controllers • National Semiconductor NS16450 and NS16550A serial communication controllers • Motorola MC146818 Time of Day Clock command and status (CMOS reorganized) • Intel 8254 timer, driven from a 1.193 MHz clock (channels 0,1, and 2) • Intel 8237 DMA controller, except for the Command and Request registers and the Rotate and Mask functions; the Mode register is partially supported • Intel 8272 or 82077 diskette drive controllers • Intel 8042 keyboard controller at addresses hex 0060 and hex 0064 • All video standards using VGA, enhanced graphics adapter (EGA), color graphics adapter (CGA), monochrome graphics adapter (MDA), and Hercules modes • Parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode Use this information to develop application programs. Whenever possible, use the BIOS as an interface to hardware to provide maximum compatibility and portability of applications among systems. Hardware interrupts Hardware interrupts are level-sensitive for PCI interrupts. The interrupt controller clears the in-service register bit when the interrupt routine sends an End-of-Interrupt (EOI) command to the controller. The EOI command is sent regardless of whether the incoming interrupt request to the controller is active or inactive. The interrupt-in-progress latch is readable at an I/O address bit position. This latch is read during the interrupt service routine and might be reset by the read operation or it might require an explicit reset. Note: For performance and latency considerations, designers might want to limit the number of devices sharing an interrupt level. With level-sensitive interrupts, the interrupt controller requires that the interrupt request be inactive at the time the EOI command is sent; otherwise, a new interrupt request will be detected. To avoid this, a level-sensitive interrupt handler must clear the interrupt condition (usually by a read or write operation to an I/O port on the device causing the interrupt). After processing the interrupt, the interrupt handler does the following: 1. Clears the interrupt 2. Waits one I/O delay 3. Enables the interrupt through the Set Interrupt Enable Flag command Hardware interrupt IRQ9 is defined as the replacement interrupt level for the cascade level IRQ2. Program interrupt sharing is implemented on IRQ2, interrupt hex 0A. The © Copyright IBM Corp. 2000 27