Lenovo PC 300PL Techical Information Manual - Page 14

PCI bus, IDE bus master interface, USB interface, AT Attachment Interface with, Extensions

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Chapter 2. System board features PCI bus The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI bus are: Integrated arbiter with multitransaction PCI arbitration acceleration hooks Zero-wait-state, microprocessor-to-PCI write interface for high-performance graphics Built-in PCI bus arbiter with support for up to five masters Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers Conversion of back-to-back sequential microprocessor-to-PCI memory write to PCI burst write PCI-to-DRAM posting 18 Dwords PCI-to-DRAM up to 100+ MB/sec bandwidth Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle PCI 2.2 compliant Delayed transaction PCI parity checking and generation support IDE bus master interface The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with Extensions. The bus master for the IDE interface is integrated into the I/O hub of the Intel 820 chip set. The chip set is PCI 2.2 compliant. It connects directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and IDE bus. The chip set is capable of supporting PIO mode 0-4 devices and IDE DMA mode 0-3 devices, ATA 66 transfers up to 66 megabytes per second (MBps). The IDE devices receive their power through a four-position power cable containing +5, +12, and ground voltage. When devices are added to the IDE interface, one device is designated as the master device and another is designated as the slave or subordinate device. These designations are determined by switches or jumpers on each device. There are two IDE ports, one designated Primary and the other Secondary, allowing for up to four devices to be attached. The total number of physical IDE devices is determined by the mechanical package. For the IDE interface, no resource assignments are given in the system memory or the direct memory access (DMA) channels. For information on the resource assignments, see "Input/output address map" on page 36 and Figure 38 on page 40 (for IRQ assignments). Two connectors are provided on the riser card for the IDE interface. For information on the connector pin assignments, see "IDE connectors" on page 30. USB interface Universal Serial Bus (USB) technology is a standard feature of the computer. The system board provides the USB interface with two connectors integrated into the ICH1 (I/O hub) in the chip set. A USB-enabled device can attach to a connector, and if that device is a hub, multiple peripheral devices can attach to the hub and be used by the system. The USB connectors use Plug and Play technology for installed devices. The speed of the USB is up to 12 MB/sec with a maximum of 127 peripheral devices. The USB is compliant with Universal Host Controller Interface Guide 1.0. 6 Technical Information Manual

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Chapter 2.
System board features
PCI bus
The fully synchronous 33 MHz PCI bus originates in the chip set.
Features of the PCI bus are:
±
Integrated arbiter with multitransaction PCI arbitration acceleration hooks
±
Zero-wait-state, microprocessor-to-PCI write interface for high-performance graphics
±
Built-in PCI bus arbiter with support for up to five masters
±
Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
±
Conversion of back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
±
PCI-to-DRAM posting 18 Dwords
±
PCI-to-DRAM up to 100+ MB/sec bandwidth
±
Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle
±
PCI 2.2 compliant
±
Delayed transaction
±
PCI parity checking and generation support
IDE bus master interface
The system board incorporates a PCI-to-IDE interface that complies with the
AT Attachment Interface with
Extensions
.
The bus master for the IDE interface is integrated into the I/O hub of the Intel 820 chip set.
The chip set
is PCI 2.2 compliant.
It connects directly to the PCI bus and is designed to allow concurrent operations on
the PCI bus and IDE bus.
The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA
mode 0–3 devices, ATA 66 transfers up to 66 megabytes per second (MBps).
The IDE devices receive their power through a four-position power cable containing +5, +12, and ground
voltage.
When devices are added to the IDE interface, one device is designated as the master device and
another is designated as the slave or subordinate device.
These designations are determined by switches
or jumpers on each device.
There are two IDE ports, one designated Primary and the other Secondary,
allowing for up to four devices to be attached.
The total number of physical IDE devices is determined by
the mechanical package.
For the IDE interface, no resource assignments are given in the system memory or the direct memory
access (DMA) channels.
For information on the resource assignments, see “Input/output address map” on
page
36 and Figure
38 on page
40 (for IRQ assignments).
Two connectors are provided on the riser card for the IDE interface.
For information on the connector pin
assignments, see “IDE connectors” on page
30.
USB interface
Universal Serial Bus (USB) technology is a standard feature of the computer.
The system board provides
the USB interface with two connectors integrated into the ICH1 (I/O hub) in the chip set.
A USB-enabled
device can attach to a connector, and if that device is a hub, multiple peripheral devices can attach to the
hub and be used by the system.
The USB connectors use Plug and Play technology for installed devices.
The speed of the USB is up to 12
MB/sec with a maximum of 127 peripheral devices.
The USB is
compliant with Universal Host Controller Interface Guide 1.0.
6
Technical Information Manual