MSI A55M User Guide - Page 27

MS-7786 tRAS This setting determines the time RAS takes to read from and write to memory cell. tRC The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. tRTP Time interval between a read and a precharge command. tWR Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. tRRD Specifies the active-to-active delay of different banks. tWTR Minimum time interval between the end of write data burst and the start of a column-read command. It allows I/O gating to overdrive sense amplifiers before read command starts. tRFC0/ 1 These settings determine the time RFC0/1 takes to read from and write to a memory cell. tWCL This item is used to set the tWCL (Write CAS Latency) timing. tFAW This item is used to set the tFAW (four activate window delay) timing. tREF This item is used to set the tREF (refresh rate) timing. Advanced Channel 1/ 2 Timing Configuration Press to enter the sub-menu. And you can set the advanced memory timing for each channel. tRWTT0/ tWRRD/ tWRWR/ tRDRD These items is used to set the memory timings for memory channel 1/ 2. Bank Interleaving Bank Interleaving is an important parameter for improving overclocking capability of memory. It allows system to access multiple banks simultaneously. DRAM Voltage This item is used to adjust the memory voltage. 27