MSI E7500 User Manual - Page 53

DRAM Timing Con CAS Latency Time, Active to Precharge Delay, DRAM RAS# Precharge, DRAM Data

Get MSI E7500 PDF manuals and user guides View all MSI E7500 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 53 highlights

Chapter 3 modules installed on the system. DRAM Timing Configure Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM on the DRAM module. Setting to By SPD enables DRAM timing to be determined automatically by BIOS based on the configurations on the SPD. Selecting Manual allows users to configure these fields manually. CAS Latency Time This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: 1.5, 2, 2.5 (clocks). 1.5 (clocks) increases the system performance the most while 2.5 (clocks) provides the most stable performance. Active to Precharge Delay The field specifies the idle cycles before precharging an idle bank. Settings: 7, 6, 5 (clocks). DRAM RAS# to CAS# Delay This field allows you to set the number of cycles for a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from or refreshed. Fast speed offers faster performance while slow speed offers more stable performance. Settings: 3, 2 (clocks). DRAM RAS# Precharge This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: 3, 2 (clocks). DRAM Data Integrity Mode Select ECC (Error-Correcting Code) or Non-ECC according to the type of installed DRAM. System BIOS Cacheable Selecting Enabled allows caching of the system BIOS ROM at F0000hFFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result. Setting options: 3-14

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
Chapter 3
3-14
modules installed on the system.
DRAM Timing Configure
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module.
Setting to
By SPD
enables DRAM
timing to be determined automatically by BIOS based on the configura-
tions on the SPD.
Selecting
Manual
allows users to configure these fields
manually.
CAS Latency Time
This controls the timing delay (in clock cycles) before SDRAM starts a
read command after receiving it.
Settings:
1.5
,
2
,
2.5
(clocks).
1.5
(clocks) increases the system performance the most while
2.5
(clocks)
provides the most stable performance.
Active to Precharge Delay
The field specifies the idle cycles before precharging an idle bank.
Settings:
7
,
6
,
5
(clocks).
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay
between the CAS and RAS strobe signals, used when DRAM is written
to, read from or refreshed.
Fast speed offers faster performance while
slow speed offers more stable performance.
Settings:
3
,
2
(clocks).
DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS)
to be allowed to precharge.
If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data.
This item applies only when synchro-
nous DRAM is installed in the system.
Available settings:
3
,
2
(clocks).
DRAM Data Integrity Mode
Select
ECC
(Error-Correcting Code) or
Non-ECC
according to the type of
installed DRAM.
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance.
However, if any program
writes to this memory area, a system error may result.
Setting options: