Sharp A260 Service Manual - Page 33

UX-A260U 5) Integrated Analog Control Resisters for 20438 The 20438 IA can be used as a Primary Integrated Analog (PIA) codec or as a Secondary Integrated Analog (SIA) codec, depending on the signal connection with the SCE Controller ASIC device. In the SCE100 product, both the PIA and the SIA are packaged external to the SCE Controller device, whereas in the SCE214V, the PIA is packaged with the SCE214V Controller and the SIA is external. The 20438 IA provides gain, filtering, internal analog switching, and an internally sourced microphone bias output. The IA is controlled by three control registers and an address register located in internal RAM space which are accessed via the modem interface memory. These registers provide individual controls for the IA's inputs, outputs, gain settings, and switching. The registers are located in internal DSP RAM. Each bit of each 8-bit IA control register has exactly the same meaning for the PIA and the SIA. The LSB of each 16-bit address contents is used to control the PIA. The MSB of each 16-bit address contents is used to control the SIA. The following table the PIA/SIA control register RAM access code. Register SBRAMx BRx Crx IACR1 0 0 0 IOx AREXx ADDx PIA Reg* SIA Reg* 0 0 D0 0 1 IACR2 0 0 0 0 0 D4 0 1 IACR3 0 0 0 0 0 D5 0 1 IAADD 0 0 0 0 0 CE 0, 1 0, 1 NOTES: *Registers to use when x=1. When x=2, add 10h. • For changes made to IACR1 to be effective, the host must write to IAADD with a value of 0002h. • For changes made to IACR2 to be effective, the host must write to IAADD with a value of 0006h. • For changes made to IACR3 to be effective, the host must write to IAADD with a value of 0007h. Configuration default values are shown below. CONFIGURATION DEFAULT VALUE IACR1 IACR2 IACR3 V.17/V.33 1D9Eh 0008h 0000h V.29 1D9Eh 0008h 0000h V.27ter 1D9Eh 0008h 0000h V.21 Ch. 2 1D9Eh 0008h 0000h V.23/Caller ID 1D9Eh 0008h 0000h Tone Transmit/Detect 1D9Eh 0008h 0000h Voice/Audio Codec 0D16h 0008h 0000h Speakerphone 0D16h 0008h 0000h The following signal flow block diagram is for a signal IA and it applies to both PIA and SIA. MICP LINE IN ENABLE MIC ENABLE MIC/LINE SELECT MICM LINEIN GAIN LPF 0, 20, 25, 30 dB(MIC IN) 0dB(LINE IN) ADC 0, +4 dB SOUT LINE OUT ENABLE LINE OUT LINE DRIVER LINE IN SELECT (1,0) (1,1) (0,0) Mute, 0, -6, -12 dB SPKRP SPKRM SPEAKER DRIVER RT Loop (0,0) DAC SIN (1,0) (0,1) 0, 6 dB SPEAKER OUT ENABLE (1,1) Fig. 3 PIA/SIA Signal Flow Control 5 - 5