Sony PCV-LX910 System Reference Manual - Page 85

SDRAM RAS to CAS Delay, VGA Shared Memory Size

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CMOS Setup Options 71 Chip Configuration Sub-Menu SDRAM Timing SDRAM CAS Latency SDRAM RAS to CAS Delay SDRAM RAS Precharge Time Refresh RAS Assertion Refresh Queue Depth SDRAM Refresh Mode Memory Hole At Address Video Memory Cache Mode Graphics Aperture Size VGA Shared Memory Size [By SPD] User Define [3 T] [4 T] [3 T] [5 T] 4 T 6 T 7 T [12] 0 4 8 [Simultaneous] Staggered 1T [None] 15 M-16 M 14 M-16 M 12 M-16 M [USWC] UC [64 MB] 128 MB 256 MB 4 MB 8 MB 16 MB 32 MB [16 MB] 8 MB 32 MB 64 MB 2 MB 4 MB

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CMOS Setup Options
71
Chip Configuration Sub-Menu
SDRAM Timing
[By SPD]
User Define
SDRAM CAS Latency
[3 T]
SDRAM RAS to CAS Delay
[4 T]
SDRAM RAS Precharge Time
[3 T]
Refresh RAS Assertion
[5 T]
4 T
6 T
7 T
Refresh Queue Depth
[12]
0
4
8
SDRAM Refresh Mode
[Simultaneous]
Staggered 1T
Memory Hole At Address
[None]
15 M-16 M
14 M-16 M
12 M-16 M
Video Memory Cache Mode
[USWC]
UC
Graphics Aperture Size
[64 MB]
128 MB
256 MB
4 MB
8 MB
16 MB
32 MB
VGA Shared Memory Size
[16 MB]
8 MB
32 MB
64 MB
2 MB
4 MB