Asus PRL-DLS PRL-DLS User Manual - Page 85

Chip Configuration

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4.4.1 Chip Configuration Video Memory Cache Mode [UC] USWC (uncacheable, speculative write combining) is a new cache technology for the video memory of the processor. It can greatly improve the display speed by caching the display data. You must set this to UC (uncacheable) if your display card cannot support this feature; otherwise your system may not boot. Configuration options: [UC] [USWC] Onboard PCI IDE [All] You can select to enable the primary, secondary, tertiary IDE channel, all channels, or disable all channels. Configuration options: [All] [Primary\Secondary] [Primary\Tertiary] [Primary] [Secondary\Tertiary\ [Secondary] [Tertiary] [Disabled] DDR DQS Delay TAP in DEC [5] Default setting is 5. User settings are from 0 to 96. The last setting, 96, is for auto selection. Configuration options: [0...96] ASUS PRL-DLS motherboard user guide 4-17

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ASUS PRL-DLS motherboard user guide
4-17
4.4.1
Chip Configuration
Video Memory Cache Mode [UC]
USWC (uncacheable, speculative write combining) is a new cache
technology for the video memory of the processor. It can greatly improve
the display speed by caching the display data. You must set this to UC
(uncacheable) if your display card cannot support this feature; otherwise
your system may not boot. Configuration options: [UC] [USWC]
Onboard PCI IDE [All]
You can select to enable the primary, secondary, tertiary IDE channel, all
channels, or disable all channels. Configuration options: [All]
[Primary\Secondary] [Primary\Tertiary] [Primary] [Secondary\Tertiary\
[Secondary] [Tertiary] [Disabled]
DDR DQS Delay TAP in DEC [5]
Default setting is 5. User settings are from 0 to 96. The last setting, 96, is
for auto selection. Configuration options: [0...96]