Fluke 123B/S Service Manual - Page 33

3 Circuit Descriptions 3.2 Block Diagram Note External triggers, supplied via the optical interface RXDA line, are buffered by the P-ASIC, and then supplied to the D-ASIC (RXD signal). The TRIG-A input is also used for capacitance measurements, as described in Section 3.2.1. The T-ASIC includes a constant current source for resistance and capacitance measurements. The current is supplied via the GENOUT output and the Ω/F relays to the unknown resistance Rx or capacitance Cx connected to Input A. The SENSE signal senses the voltage across Cx and controls a CLAMP circuit in the T-ASIC. This circuit limits the voltage on Input A at capacitance measurements. The protection circuit prevents the T-ASIC from being damaged by voltages supplied to the input during resistance or capacitance measurements. For probe adjustment, a voltage generator circuit in the T-ASIC can provide a square wave voltage via the GENOUT output to the Input A connector. The T-ASIC contains opamps to derive reference voltages from a 1.23V reference source. The gain factors for these opamps are determined by resistors in the REF GAIN circuit. The reference voltages are supplied to various circuits. The T-ASIC also controls the Channel A and B AC/DC input coupling relays, and the Ω/F relays. Control data for the T-ASIC are provided by the D-ASIC via the SDAT and SCLK serial communication lines. 3.2.3 Digital Circuit The D-ASIC includes a micro processor, ADC sample acquisition logic, trigger processing logic, display and keyboard control logic, I/O ports, and various other logic circuits. The instrument software is stored in the FlashROM, the RAM is used for temporary data storage. The RESET ROM circuit controls the operating mode of the FlashROM (reset, programmable, operational). For Voltage and Resistance measurements, the conditioned Input A/ Input B voltages are supplied to the ADC-A and ADC-B ADC. The voltages are sampled, and digitized by the ADC's. The output data of the ADC's are acquired and processed by the D-ASIC. For capacitance measurements, the ALLTRIG signal generated by the T-ASIC, is used. The D-ASIC counts the ALLTRIG signal pulse width, which is proportional to the unknown capacitance. The DPWM-BUS (Digital Pulse Width Modulation) supplies square wave signals with a variable duty cycle to the PWM FILTERS circuit (RC filters). The outgoing APWMBUS (Analog PWM) provides analog signals of which the amplitude is controlled by the D-ASIC. These voltages are used to control e.g. the trace positions (C-ASIC), the trigger levels (T-ASIC), and the battery charge current (P-ASIC). In random sampling mode (time base faster than 1 µs/div.), a trace is built-up from several acquisition cycles. During each acquisition, a number of trace samples are placed as pixels in the LCD. The RANDOMIZE circuit takes care that the starting moment of each acquisition cycle (trigger release signal HOLDOFF goes low) is random. This prevents that at each next acquisition the trace is sampled at the same time positions, and that the displayed trace misses samples at some places on the LCD. The D-ASIC supplies control data and display data to the LCD module. The LCD module is connected to the main board via connector X453. It consists of the LCD, LCD 3-5