Fluke 123B/S Service Manual - Page 42

RS232, Backlight Converter, voltage V600, V602, L600, C602.

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123/124 Service Manual 3-14 on pin 3 of the comparator step wise, by changing the duty cycle of the PWM signal SADCLEVD. The comparator output SLOWADC is monitored by the D-ASIC, who knows now if the previous input voltage step caused the comparator output to switch. By increasing the voltage steps, the voltage level can be approximated within the smallest possible step of the SADCLEV voltage. From its set SADCLEVD duty cycle, the DASIC knows voltage level of the selected input. RS232 (Refer to Figure 9-6) The optical interface is used for two purposes: • enable serial communication (RS232) between the test tool and a PC or printer • enable external triggering using the Isolated Trigger Probe ITP120 The received data line RXDA (P-ASIC pin 75) is connected to ground via a 20 kΩ resistor in the P-ASIC. If no light is received by the light sensitive diode H522, the RXDA line is +200 mV, which corresponds to a "1" (+3V) on the RXD (P-ASIC output pin 76) line. If light is received, the light sensitive diode will conduct, and the RXDA line goes low (0...-0.6V), which corresponds to a "0" on the RXD line. The level on the RXDA line is compared by a comparator in the P-ASIC to a 100 mV level. The comparator output is the RXD line, which is supplied to the D-ASIC for communication, and for external triggering. The D-ASIC controls the transmit data line TXD. If the line is low, diode H521 will emit light. The supply voltage for the optical interface receive circuit (RXDA), is the +3V3SADC voltage. The +3V3SADC voltage is present if the test tool is turned on, or if the Power Adapter is connected (or both). So if the Power Adapter is present, serial communication is always possible, even when the test tool is off. Backlight Converter (Refer to Figure 9-7) The LCD back light is provided by a ∅2.4 mm fluorescent lamp in LCD unit. The back light converter generates the 300-400 Vpp ! supply voltage. The circuit consist of: • A pulse width modulated (PWM) buck regulator to generate a variable, regulated voltage (V600, V602, L600, C602). • A zero voltage switched (ZVS) resonant push-pull converter to transform the variable, regulated voltage into a high voltage AC output (V601, T600). The PWM buck regulator consists of FET V600, V602, L600, C602, and a control circuit in N600. FET V600 is turned on and off by a square wave voltage on the COUT output of N600 pin 14). By changing the duty cycle of this signal, the output on C602 provides a variable, regulated voltage. The turn on edge of the COUT signal is synchronized with each zero detect. Outputs AOUT and BOUT of N600 provide complementary drive signals for the pushpull FETs V601a/b (dual FET). If V601a conducts, the circuit consisting of the primary winding of transformer T600 and C608, will start oscillating at its resonance frequency. After half a cycle, a zero voltage is detected on pin 9 (ZD) of N600, V601a will be turned off, and V601b is turned on. This process goes on each time a zero is detected. The secondary current is sensed by R600/R604, and fed back to N600 pin 7 and pin 4 for regulation of the PWM buck regulator output voltage. The BACKBRIG signal supplied by the D-ASIC provides a pulse width modulated (variable duty cycle) square wave. By changing the duty cycle of this signal, the average on-resistance of V604 can be changed. This will change the secondary current, and thus the back light intensity. The voltage on the "cold" side of the lamp is limited by V605 and V603. This limits the emission of

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123/124
Service Manual
3-14
on pin 3 of the comparator step wise, by changing the duty cycle of the PWM signal
SADCLEVD.
The comparator output SLOWADC is monitored by the D-ASIC, who
knows now if the previous input voltage step caused the comparator output to switch.
By
increasing the voltage steps, the voltage level can be approximated within the smallest
possible step of the SADCLEV voltage.
From its set SADCLEVD duty cycle, the D-
ASIC knows voltage level of the selected input.
RS232
(Refer to Figure 9-6)
The optical interface is used for two purposes:
•
enable serial communication (RS232) between the test tool and a PC or printer
•
enable external triggering using the Isolated Trigger Probe ITP120
The received data line RXDA (P-ASIC pin 75) is connected to ground via a 20 k
Ω
resistor in the P-ASIC.
If no light is received by the light sensitive diode H522, the RXDA line is +200 mV,
which corresponds to a “1” (+3V) on the RXD (P-ASIC output pin 76) line.
If light is received, the light sensitive diode will conduct, and the RXDA line goes low
(0...-0.6V), which corresponds to a “0” on the RXD line.
The level on the RXDA line is compared by a comparator in the P-ASIC to a 100 mV
level.
The comparator output is the RXD line, which is supplied to the D-ASIC for
communication, and for external triggering.
The D-ASIC controls the transmit data line TXD.
If the line is low, diode H521 will
emit light.
The supply voltage for the optical interface receive circuit (RXDA), is the +3V3SADC
voltage.
The +3V3SADC voltage is present if the test tool is turned on, or if the Power
Adapter is connected (or both).
So if the Power Adapter is present, serial
communication is always possible, even when the test tool is off.
Backlight Converter
(Refer to Figure 9-7)
The LCD back light is provided by a
∅
2.4 mm fluorescent lamp in LCD unit.
The back
light converter generates the 300-400 Vpp ! supply voltage.
The circuit consist of:
•
A pulse width modulated (PWM) buck regulator to generate a variable, regulated
voltage (V600, V602, L600, C602).
•
A zero voltage switched (ZVS) resonant push-pull converter to transform the
variable, regulated voltage into a high voltage AC output (V601, T600).
The PWM buck regulator consists of FET V600, V602, L600, C602, and a control circuit
in N600.
FET V600 is turned on and off by a square wave voltage on the COUT output
of N600 pin 14).
By changing the duty cycle of this signal, the output on C602 provides
a variable, regulated voltage.
The turn on edge of the COUT signal is synchronized with
each zero detect.
Outputs AOUT and BOUT of N600 provide complementary drive signals for the push-
pull FETs V601a/b (dual FET).
If V601a conducts, the circuit consisting of the primary
winding of transformer T600 and C608, will start oscillating at its resonance frequency.
After half a cycle, a zero voltage is detected on pin 9 (ZD) of N600, V601a will be
turned off, and V601b is turned on.
This process goes on each time a zero is detected.
The secondary current is sensed by R600/R604, and fed back to N600 pin 7 and pin 4 for
regulation of the PWM buck regulator output voltage.
The BACKBRIG signal supplied
by the D-ASIC provides a pulse width modulated (variable duty cycle) square wave.
By
changing the duty cycle of this signal, the average on-resistance of V604 can be changed.
This will change the secondary current, and thus the back light intensity.
The voltage on
the “cold” side of the lamp is limited by V605 and V603.
This limits the emission of