Fluke 123B/S Service Manual - Page 53

Digital Circuit and ADC's, Tracerot Signal, AC/DC Relay and, F Relay Control, SCLK, SDAT Signals

Get Fluke 123B/S PDF manuals and user guides View all Fluke 123B/S manuals
Add to My Manuals
Save this manual to your list of manuals

Page 53 highlights

3 Circuit Descriptions 3.3 Detailed Circuit Descriptions Amplifier 3 and 4 and connected resistors supply the REFADCT and REFADCB reference voltages for the ADC's. Both voltages directly influence the gain accuracy of the ADC's. The T-ASIC can select some of the reference voltages to be output to pin 8 (REFATT). The REFATT voltage is used for internal calibration of the input A and B overall gain. Tracerot Signal The T-ASIC generates the TRACEROT signal, used by the C-ASIC's. Control signals TROTRST and TROTCLK are provided by the D-ASIC. AC/DC Relay and Ω/F Relay Control The Channel A/B AC/DC relays K171/K271, and the Channel A Ω/F relay K173 are controlled by the T-ASIC output signals ACDCA (pin 22), ACDCB (pin 23) and OHMA (pin 24). SCLK, SDAT Signals T-ASIC control data, e.g. for trigger source/mode/edge selection and relay control, are provided by the D-ASIC via the SCLK and SDAT serial control lines.. 3.3.4 Digital Circuit and ADC's Refer to the Fluke 123/124 block diagram Figure 3-1, and circuit diagrams in Figure 9-5 (Digital Circuit) and Figure 9-3 (ADC-section). The Digital part is built up around the D-ASIC HS353063 (D471A). It provides the following functions: • ADC data acquisition for traces and numerical readings • Trigger processing • Pulse width measurements, e.g. for capacitance measurement function • Microprocessor, Flash EPROM and RAM control • Display control • Keyboard control, ON/OFF control • Miscellaneous functions, as PWM signal generation, SDA-SCL serial data control, probe detection, Slow ADC control, serial RS232 interface control, buzzer control, etc. The D-ASIC is permanently powered by the +3V3GAR voltage supplied by the Power Circuit if at least the battery pack is present (+VR after filtering). The P-ASIC indicates the status of the +3V3GAR voltage via the VDDVAL line connected to D-ASIC pin N2. If +3V3GAR is >3V, VDDVAL is high, and the D-ASIC will start-up. As a result the DASIC functions are operative regardless of the test tool's is ON/OFF status. The RAM supply voltage +VR and the FlashROM supply voltage +VF are also derived from +3V3GAR. Analog to Digital Conversion For voltage and resistance measurements, the Input A/B (B for voltage only) signal is conditioned by the C-ASIC to 150 mV/division. Zero and gain measurement are done to eliminate offset and gain errors. The C-ASIC output voltage is supplied to the Channel A/B ADC (D401/D451 pin 27). The ADC samples the analog voltage, and converts it 3-25

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
Circuit Descriptions
3.3 Detailed Circuit Descriptions
3
3-25
Amplifier 3 and 4 and connected resistors supply the REFADCT and REFADCB
reference voltages for the ADC’s.
Both voltages directly influence the gain accuracy of
the ADC’s.
The T-ASIC can select some of the reference voltages to be output to pin 8 (REFATT).
The REFATT voltage is used for internal calibration of the input A and B overall gain.
Tracerot Signal
The T-ASIC generates the TRACEROT signal, used by the C-ASIC’s.
Control signals
TROTRST and TROTCLK are provided by the D-ASIC.
AC/DC Relay and
Ω
/F Relay Control
The Channel A/B AC/DC relays K171/K271, and the Channel A
Ω
/F relay K173 are
controlled by the T-ASIC output signals ACDCA (pin 22), ACDCB (pin 23) and OHMA
(pin 24).
SCLK, SDAT Signals
T-ASIC control data, e.g. for trigger source/mode/edge selection and relay control, are
provided by the D-ASIC via the SCLK and SDAT serial control lines..
3.3.4 Digital Circuit and ADC’s
Refer to the Fluke 123/124 block diagram Figure 3-1, and circuit diagrams in Figure 9-5
(Digital Circuit) and Figure 9-3 (ADC-section).
The Digital part is built up around the D-ASIC HS353063 (D471A).
It provides the
following functions:
•
ADC data acquisition for traces and numerical readings
•
Trigger processing
•
Pulse width measurements, e.g. for capacitance measurement function
•
Microprocessor, Flash EPROM and RAM control
•
Display control
•
Keyboard control, ON/OFF control
•
Miscellaneous functions, as PWM signal generation, SDA-SCL serial data control,
probe detection, Slow ADC control, serial RS232 interface control, buzzer control,
etc.
The D-ASIC is permanently powered by the +3V3GAR voltage supplied by the Power
Circuit if at least the battery pack is present (+VR after filtering). The P-ASIC indicates
the status of the +3V3GAR voltage via the VDDVAL line connected to D-ASIC pin N2.
If +3V3GAR is >3V, VDDVAL is high, and the D-ASIC will start-up. As a result the D-
ASIC functions are operative regardless of the test tool’s is ON/OFF status.
The RAM supply voltage +VR and the FlashROM supply voltage +VF are also derived
from +3V3GAR.
Analog to Digital Conversion
For voltage and resistance measurements, the Input A/B (B for voltage only) signal is
conditioned by the C-ASIC to 150 mV/division.
Zero and gain measurement are done to
eliminate offset and gain errors.
The C-ASIC output voltage is supplied to the Channel
A/B ADC (D401/D451 pin 27).
The ADC samples the analog voltage, and converts it