Fluke 123B/S Service Manual - Page 54

123/124 Service Manual into an 8-bit data byte (D0-D7). The data are read and processed by the D-ASIC, see below "ADC data Acquisition". The sample rate depends on the sample clock supplied to pin 15. The sample rate is 5 MHz or 25 MHz, depending on the instrument mode. The ADC-A input signal is sampled by sample clock SMPCLK_A; ADC-B by SMPCLK_B. Both sample clocks are generated by the D-ASIC. SMPCLK_B is also used for synchronisation of the Trigger Circuit (B is choosen because of the printed circuit board track layout). The reference voltages REFADCT and REFADCB determine the input voltage swing that corresponds to an output data swing of 00000000 to 11111111 (D0-D7). The reference voltages are supplied by the reference circuit on the Trigger part. The ADC output voltages MIDADC_A/B are supplied to the C-ASIC's (input pin 28), and are added to the conditioned input signal. The MIDADC voltage matches the middle of the C-ASIC output swing to the middle of the ADC input swing. The ADC's are supplied with +3V3ADCD (supply for digital section; derived from +3V3D) and +3V3ADCA (supply for analog section; derived from +3V3A). ADC data acquisition for traces and numerical readings During an acquisition cycle, ADC samples are acquired to complete a trace on the LCD. Numerical readings (METER readings) are derived from the trace. So in single shot mode a new reading becomes available when a new trace is started. The test tool software starts an acquisition cycle. The D-ASIC acquires data from the ADC, and stores them internally in a cyclic Fast Acquisition Memory (FAM). The DASIC also makes the HOLDOFF line low, to enable the T-ASIC to generate the trigger signal TRIGDT. The acquisition cycle is stopped if the required number of samples is acquired. From the FAM the ADC data are moved to the RAM D475. The ADC data stored in the RAM are processed and represented as traces and readings. Triggering (HOLDOFF, TRIGDT, Randomize) To start a new trace, the D-ASIC makes the HOLDOFF signal low. Now the T-ASIC can generate the trigger signal TRIGDT. For signal frequencies higher than the system clock frequency, and in the random repetitive sampling mode, no fixed time relation between the HOLDOFF signal and the system clock is allowed. The RANDOMIZE circuit desynchronizes the HOLDOFF from the clock, by phase modulation with a LF ramp signal. Trigger qualifying (ALLTRIG, TRIGQUAL) The ALLTRIG signal supplied by the T-ASIC contains all possible triggers. For normal triggering, the T-ASIC uses ALLTRIG to generate the final trigger TRIGDT. For qualified triggering (e.g. TV triggering), the D-ASIC returns a qualified, e.g. each nth , trigger pulse to the T-ASIC (TRIGQUAL). Now the T-ASIC derives the final trigger TRIGDT from the qualified trigger signal TRIGQUAL. Capacitance measurements (ALLTRIG) As described in Section 3.3.2, capacitance measurements are based on measuring the capacitor charging time using a known current. The ALLTRIG pulse signal represents the charging time. The time is counted by the D-ASIC Microprocessor The D-ASIC includes a microprocessor with a 16 bit data bus. The instrument software is loaded in a 16 Mb Flash ROM D474. 3-26