Foxconn M61PMV English Manual. - Page 33

► CKE Base Power Down Mode

Get Foxconn M61PMV PDF manuals and user guides View all Foxconn M61PMV manuals
Add to My Manuals
Save this manual to your list of manuals

Page 33 highlights

3 ► DCTs Mode (Appears only when CPU support) DCT stands for DRAM Controller. Ganged refers to the use of both DRAM controllers within a memory controller acting in concert to access memory. For a description of ganged (128-bit DRAM data width) and unganged (64-bit DRAM data width) DRAM modes : Ganged channels (DDR2) : ■ DCT channels A and B can be ganged as a single logical 128-bit DIMM. ■ Offers highest DDR2 bandwidth. ■ Requires both DIMMs in a logical pair to have identical size and timing parameters, both DCTs programmed identically. Unganged channels ■ DCT channels A and B operate as two completely independent 64-bit channels (both channels operate at the same frequency). ■ Reduce DRAM page conflicts - more concurrent open dram pages . ■ Better bus efficiency. Burst lengths supported When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each DCT in order. ► CKE Base Power Down Mode This item allows you to enable or disable the CKE base power down mode. ► CKE Base Power Down CKE power down mode selection. ► Memclock Tri-stating Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. ► Memory Hole Remapping This item is used to enable/disable memory remapping around memory hole. PCI doesn't actually care much which addresses are used, but by convention the PC platform puts them at the top of the 32-bit address space. For many years it wasn't possible or practical to put that much RAM into a PC. But now it is, so it's up to the memory controller and host bridge to figure out what to do. Many systems cause that high RAM to simply be ignored, resulting in the loss of effective RAM. More complex systems will take the RAM that would occupy that 3.5-4GB address space and re-map it into the 4.0-4.5 address space. The RAM doesn't care because it's just an array of storage cells, it's up to the memory controller to associate addresses with those storage cells. Of course, that only works if you're using a 64-bit (or 32-bit physical address extension (PAE) enabled) OS that can deal with physical addresses larger than 32 bits.Once this option is enabled, the BIOS can see 4096MB of memory. ► Auto Optimize Bottom IO Auto optimize maximum DRAM size when kernel assigns PCI resources done. ► Bottom of [31:24] IO Space Select bottom of [31:24] IO space manually when "Auto Optimize Bottom IO" option is disabled. ► Bottom of UMA DRAM [31:24] This is a memory allocation method addition to the Unified Memory Architecture (UMA) concept. Normally, select the default value. 26

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
3
26
► DCTs Mode
(Appears only when CPU support)
DCT stands for DRAM Controller.
Ganged refers to the use of both DRAM controllers within a memory controller acting in con-
cert to access memory. For a description of ganged (128-bit DRAM data width) and unganged
(64-bit DRAM data width) DRAM modes :
Ganged channels (DDR2) :
■
DCT channels A and B can be ganged as a single logical 128-bit DIMM.
■
Offers highest DDR2 bandwidth.
■
Requires both DIMMs in a logical pair to have identical size and timing parameters, both
DCTs programmed identically.
Unganged channels
■
DCT channels A and B operate as two completely independent 64-bit channels (both chan-
nels operate at the same frequency).
■
Reduce DRAM page conflicts – more concurrent open dram pages .
■ Better bus efficiency.
Burst lengths supported
When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each
DCT in order.
► CKE Base Power Down Mode
This item allows you to enable or disable the CKE base power down mode.
► CKE Base Power Down
CKE power down mode selection.
► Memclock Tri-stating
Enables the DDR memory clocks to be tristated when alternate VID mode is enabled.
► Memory Hole Remapping
This item is used to enable/disable memory remapping around memory hole. PCI doesn't actu-
ally care much which addresses are used, but by convention the PC platform puts them at the
top of the 32-bit address space. For many years it wasn't possible or practical to put that much
RAM into a PC. But now it is, so it's up to the memory controller and host bridge to figure out
what to do.
Many systems cause that high RAM to simply be ignored, resulting in the loss of
effective RAM.
More complex systems will take the RAM that would occupy that 3.5-4GB
address space and re-map it into the 4.0-4.5 address space. The RAM doesn't care because
it's just an array of storage cells, it's up to the memory controller to associate addresses
with those storage cells. Of course, that only works if you're using a 64-bit (or 32-bit physical
address extension (PAE) enabled) OS that can deal with physical addresses larger than 32
bits.Once this option is enabled, the BIOS can see 4096MB of memory.
► Auto Optimize Bottom IO
Auto optimize maximum DRAM size when kernel assigns PCI resources done.
► Bottom of [31:24] IO Space
Select bottom of [31:24] IO space manually when "Auto Optimize Bottom IO" option is
disabled.
► Bottom of UMA DRAM [31:24]
This is a memory allocation method addition to the Unified Memory Architecture (UMA)
concept. Normally, select the default value.