HP DL360 Memory technology evolution: an overview of system memory technologie
HP DL360 - ProLiant - G3 Manual
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- HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 1
overview of system memory technologies technology brief, 8th edition Abstract...2 Introduction ...2 Basic DRAM operation ...2 DRAM storage density and power consumption 4 Memory access time ...5 System bus timing ...5 Memory of using HP-certified memory modules in ProLiant servers 23 Conclusion...23 - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 2
an overview of some the newest memory technologies that HP is evaluating for servers and workstations. The purpose is to allay some of the confusion about the performance and benefits of the dynamic random access memory (DRAM) technologies on the market. Introduction Processors use system memory to - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 3
the memory controller function integrated into processor module The memory subsystem operates at the memory bus speed. Typically, to access a DRAM cell, the memory controller sends electronic address signals that specify the row address and column address of the target cell. The memory controller - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 4
CAS Latency, the DRAM devices drive the data onto the memory bus. DRAM cannot be accessed during a refresh. If the processor makes a data request during driving CAS active before driving RAS active, is used most often. DRAM storage density and power consumption The storage capacity (density) of DRAM - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 5
bus clock controls all computer components that execute instructions or transfer data. Typically, the system chipset controls the speed, or frequency, of the system bus clock and thus regulates the traffic between the processor, main memory, PCI bus, and other peripheral buses. The bus clock is - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 6
system bus clock. The two main factors that control the speed of the memory subsystem are the memory timing and the maximum DRAM speed. The server BIOS sets the memory system speed based represents the number of clock cycles to read/write the first 64 bits and "y" represents the number of clock - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 7
memory devices and modules- developed the synchronous DRAM standard to reduce the number of system clock cycles required to read or write data. SDRAM uses a memory one memory bank is being accessed, the other bank remains ready to be accessed. This allows the processor to initiate a new memory access - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 8
system bus clock signal from having to drive all the DRAM chips. It also allows adding more memory modules to the memory bus to increase memory capacity. Figure 6. Registered DIMMs NOTE: Some CPU designs include the memory controller function integrated into processor ninth chip is used to store 4 - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 9
. To compensate for the reduction in the number of DIMM slots on a bus at higher speeds, modern chipsets employ multiple memory buses. If the total number of ranks in the populated DIMM slots exceeds the maximum number of loads the chipset can support, the server may not boot properly or it may not - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 10
problems, HP urges customers to use only HP-certified DIMMs, which are available in the memory option kits for each ProLiant server (see the "Importance of using HP-certified memory modules in ProLiant servers" section). Another important difference between single-rank and dual-rank DIMMs is cost - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 11
ECC in all HP ProLiant servers. ECC detects both single-bit and multi-bit errors in a 64-bit data word, and it corrects single-bit errors. ECC encodes information in a block of 8 bits to permit the recovery of a single-bit error. Every time data is written to memory, ECC uses a special algorithm to - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 12
in 1996. HP and most other server manufacturers use this solution in industry-standard products. Advanced ECC can correct a multi-bit error that occurs within one DRAM chip; thus, it can correct a complete DRAM chip failure. In Advanced ECC with 4-bit (x4) memory devices, each chip contributes - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 13
a failed DIMM requires powering down the system. Taking a server off line for unscheduled maintenance almost always raises operating costs-both in terms of replacement parts and in lost revenue from a server's lack of availability. Three available memory protection technologies offer failover - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 14
and reduces a system's total capacity. Nevertheless, server availability is considered the highest priority for enterprise environments. The user configures the system for the desired memory protection mode through the ROM-based Setup Utility (RBSU) contained in the BIOS. Online Spare, Mirrored, and - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 15
performance improvement in the overall system from using SDRAM, the growing performance gap between the memory and processor must be filled by more advanced memory technologies. These technologies, described on the following pages, boost the overall performance of systems using the latest high-speed - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 16
-Terminated Logic_2 (SSTL_2). This low-voltage signaling results in lower power consumption and improved heat dissipation. Stobe-based data bus SSTL_2 signaling allows DDR-1 to run at faster speeds than traditional SDRAM. In addition, DDR-1 uses a delay-locked loop (one for every 16 outputs) to - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 17
on the system memory bus. They can be used in systems that do not require high memory capacity. Registered DDR-1 DIMMs (Figure 12) place only one load per DIMM on the memory bus, regardless of how many SDRAM devices are on the module. Therefore, they are best suited for servers with very high - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 18
number of stubs and their length. This feature requires the controller to support "write leveling" on DDR-3 DIMMs. 1.5-V signaling reduces power over the Rambus naming convention the industry based the DDR-SDRAM naming convention on the memory module and offer lower latency and (relatively) low power - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 19
a stub-bus topology with parallel branches (stubs) that connect to a shared memory bus (Figure 15). Each DIMM connects to the data bus using a set of pin connectors. For the electrical signals from the memory controller to reach the DIMM bus-pin connections at the same time, all the traces must be - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 20
channel based on DRAM data rate Increasing the number of channels to compensate for the drop in capacity per channel was not a viable option due to increased cost and board complexity. System designers had two options: limit memory capacity so that fewer errors occur at higher speeds, or use slower - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 21
-chained FB-DIMMs on a single channel NOTE: AMD® Opteron® and Intel® Xeon® E55xx/X55xx CPU designs include the memory controller and clock functions integrated into processor module. When using DDR2-667 DRAM on the FB-DIMM, the peak theoretical throughput of the inbound links is 5.4 GB/s. The peak - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 22
of Rambus, and this increases product time to market. Additionally, each Rambus channel is limited to 32 devices, imposing an upper limit on memory capacity supported by a single bus. Use of repeater chips enables use of additional devices and increases potential memory capacity, but repeater chips - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 23
capabilities and requirements of the ProLiant server for which they are designated. HP memory option kits are listed in each server's user guide and in the product QuickSpecs available at www.hp.com. Conclusion The increasing performance gap between processors and memory has generated development of - HP DL360 | Memory technology evolution: an overview of system memory technologie - Page 24
to the resources listed below. Resource description JEDEC Web site Fully-Buffered DIMM technology in HP ProLiant servers Web address http://www.jedec.org http://h18004.www1.hp.com/products/servers/technology/whitepap ers/adv-technology.html#mem Call to action Send comments about this paper to
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Abstract
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2
Introduction
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2
Basic DRAM operation
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2
DRAM storage density and power consumption
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4
Memory access time
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5
System bus timing
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5
Memory bus speed
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6
Burst mode access
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6
SDRAM technology
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7
Bank interleaving
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7
Increased bandwidth
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7
Registered SDRAM modules
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8
DIMM configurations
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8
Single-sided and double-sided DIMMs
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8
Single-rank, dual-rank, and quad-rank DIMMs
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8
DIMM error detection/correction technologies
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The increasing possibility of memory errors
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Basic ECC memory
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Advanced ECC memory
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Memory protection technologies
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Online spare memory mode
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Mirrored memory mode
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Lockstep memory mode
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Memory protection mode summary
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Advanced memory technologies
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Double data rate SDRAM technologies
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DDR-1
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DDR-2
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DDR-3
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Module naming convention and peak bandwidth
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Fully-buffered DIMMs
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Rambus DRAM
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Importance of using HP-certified memory modules in ProLiant servers
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Conclusion
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For more information
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Call to action
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Memory technology evolution:
an overview of system memory technologies
technology brief, 8
th
edition