HP ProLiant BL660c Electrical signal integrity considerations for HP BladeSyst - Page 11

For double-wide switch modules, the main high-speed interface consists of two groups (eight pairs) of signals that are available from each server blade. These are used to route signals that require up to four Lanes, such as 10 GB Ethernet using the 3.125 Gbaud SERDES1 type of interface. Implementation In order to guarantee success and manage costs effectively, the BladeSystem design team separated the system into its component parts, illustrated in Figure 8, created and applied significant modeling/simulation techniques, and then verified, through empirical data, that the models accurately reflected the physical system. The team then created an extensive documentation/specification library and implemented a design review process that ensures continued adherence and success. Specific steps included the following: • Assisting the internal product teams in signal integrity best practice; providing layout/routing guidelines; including optimizations for 10Gbs • Assisting in the design and validation of top tier mezzanine and switch designs; assisting vendors with signal integrity related direction and in-house hardware measurements • Developing accurate channel models • Ensuring that the NonStop midplane can handle up to 10Gbs signaling • Developing signal integrity tools and models to help develop lower tier independent hardware vendor (IHV) solutions Achieving this level of bandwidth between bays required special attention to maintain the signal integrity of the high-speed signals. HP took three key steps to maintain signal integrity: • Using general best practices for signal integrity to minimize end-to-end signal losses across the signal midplane • Moving the power into an entirely separate backplane to independently optimize the signal midplane • Providing means to set optimal signal waveform shapes in the transmitters, depending on the topology of the end-to-end signal channel Following best practices for signal integrity was important to ensure high-speed connectivity among all server blades and interconnect modules. To aid in the design of the signal midplane, HP involved the same signal integrity experts that design the HP Superdome computers. Specifically, HP paid special attention to several best practices: • Controlling the differential impedance along each end-to-end channel on the PCBs and through the connector stages • Planning signal pin assignments so that receive signal pins are grouped together yet isolated by a ground plane from the transmit signal pins in order to minimize crosstalk • Keeping the overall channel short to minimize losses • Increasing the length of short traces in order to minimize reflections • Routing signals in groups to minimize signal skew • Reducing the number of through-hole via stubs by carefully selecting the layers to route the traces, controlling the PCB thickness, and back-drilling long via-hole stubs to minimize signal reflections 1 The 3.125 Gbaud SERDES is a serializer/deserializer (SerDes) data interface used to transmit data between chips. 11