Intel D845PEBT2 Product Guide - Page 68

Chipset Configuration Submenu, Advanced, Table 22.

Get Intel D845PEBT2 PDF manuals and user guides View all Intel D845PEBT2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 68 highlights

Intel Desktop Board D845PEBT2 Product Guide Chipset Configuration Submenu Maintenance Main Advanced Security Power Boot Exit Chipset Configuration The menu shown in Table 22 is used to configure advanced chipset features. Table 22. Chipset Configuration Submenu Feature Options ISA Enable Bit PCI Latency Timer Extended Configuration SDRAM Frequency SDRAM Timing Control • Enabled (default) • Disabled • 32 (default) • 64 • 96 • 128 • 160 • 192 • 224 • 248 • Default (default) • User Defined • Auto (default) • 200 MHz • 266 MHz • 333 MHz • Auto (default) • Manual - Aggressive • Manual - User Defined SDRAM RAS Act. To Pre. SDRAM CAS# Latency SDRAM RAS# to CAS# delay SDRAM RAS# Precharge • 8 • 7 • 6 • 5 • Auto (default) • 2.5 • 2 • Auto (default) • 4 • 3 • 2 • Auto (default) • 4 • 3 • 2 • Auto (default) Description Some older expansion devices require this to be enabled. Set PCI latency time. Chooses the default or user defined settings for the extended configuration options. Allows override of detected memory frequency value. Auto allows timings to be programmed according to the memory detected. Manual - Aggressive selects the most aggressive user defined timings. Manual - User Defined allows manual override of detected SDRAM settings. Selects length of time from read to pre-change. Selects the number of clock cycles required to address a column in memory. Selects the number of clock cycles between addressing a row and addressing a column. Selects the length of time required before accessing a new row. 68

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
Intel Desktop Board D845PEBT2 Product Guide
68
Chipset Configuration Submenu
Maintenance
Main
Advanced
Security
Power
Boot
Exit
Chipset Configuration
The menu shown in Table 22 is used to configure advanced chipset features.
Table 22.
Chipset Configuration Submenu
Feature
Options
Description
ISA Enable Bit
•
Enabled (default)
•
Disabled
Some older expansion devices require this to be
enabled.
PCI Latency Timer
•
32 (default)
•
64
•
96
•
128
•
160
•
192
•
224
•
248
Set PCI latency time.
Extended Configuration
•
Default
(default)
•
User Defined
Chooses the default or user defined settings for
the extended configuration options.
SDRAM Frequency
•
Auto (default)
•
200 MHz
•
266 MHz
•
333 MHz
Allows override of detected memory frequency
value.
SDRAM Timing Control
•
Auto (default)
•
Manual
–
Aggressive
•
Manual
–
User Defined
Auto
allows timings to be programmed according
to the memory detected.
Manual – Aggressive
selects the most aggressive
user defined timings.
Manual
–
User Defined
allows manual override of
detected SDRAM settings.
SDRAM RAS Act. To Pre.
•
8
•
7
•
6
•
5
•
Auto (default)
Selects length of time from read to pre-change.
SDRAM CAS# Latency
•
2.5
•
2
•
Auto (default)
Selects the number of clock cycles required to
address a column in memory.
SDRAM RAS# to CAS#
delay
•
4
•
3
•
2
•
Auto (default)
Selects the number of clock cycles between
addressing a row and addressing a column.
SDRAM RAS# Precharge
•
4
•
3
•
2
•
Auto (default)
Selects the length of time required before
accessing a new row.