Intel KD875PBZLKPAK10 Product Specification - Page 56

Table 17., PCI Interrupt Routing Map

Page 56 highlights

Intel Desktop Board D875PBZ Technical Product Specification Table 17. PCI Interrupt Routing Map PCI Interrupt Source PIRQA AGP connector INTA ICH5-R USB UHCI controller 1 INTA SMBus controller ICH5-R USB UHCI controller 2 AC '97 ICH5-R Audio ICH5-R LAN ICH5-R USB UHCI controller 3 ICH5-R USB UHCI controller 4 INTA ICH5-R USB 2.0 EHCI controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 INTD PCI bus connector 4 PCI bus connector 5 INTC Serial ATA/Serial ATA RAID PIRQB INTB INTB INTB INTA ICH5-R PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTB INTC INTA INTB INTB INTA INTC INTA INTD INTC INTD INTA INTB INTC INTA PIRQG INTB INTA INTD PIRQH INTD INTC INTD INTB ✏ NOTE In PIC mode, the ICH5-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 16 for the allocation of PIRQ lines to IRQ signals in APIC mode. 56

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Intel Desktop Board D875PBZ Technical Product Specification
56
Table 17.
PCI Interrupt Routing Map
ICH5-R PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
AGP connector
INTA
INTB
ICH5-R USB UHCI controller 1
INTA
SMBus controller
INTB
ICH5-R USB UHCI controller 2
INTB
AC
97 ICH5-R Audio
INTB
ICH5-R LAN
INTA
ICH5-R USB UHCI controller 3
INTC
ICH5-R USB UHCI controller 4
INTA
ICH5-R USB 2.0 EHCI
controller
INTD
PCI bus connector 1
INTD
INTA
INTB
INTC
PCI bus connector 2
INTC
INTB
INTA
INTD
PCI bus connector 3
INTD
INTA
INTB
INTC
PCI bus connector 4
INTB
INTA
INTC
INTD
PCI bus connector 5
INTC
INTA
INTD
INTB
Serial ATA/Serial ATA RAID
INTA
NOTE
In PIC mode, the ICH5-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5,
6, 7, 9, 10, 11, 12, 14, and 15).
Typically, a device that does not share a PIRQ line will have a
unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal.
Refer to Table 16 for the
allocation of PIRQ lines to IRQ signals in APIC mode.