Intel S845WD1-E Product Guide - Page 88

Table 40. I/O Map (continued) Address (hex) Description 8 bytes on an 8-byte boundary Unknown 96 contiguous bytes starting on a 128-byte divisible boundary ICH2 (ACPI + TCO) 64 contiguous bytes starting on a 64-byte divisible boundary S845WD1H server board resource 32 contiguous bytes starting on a 32-byte divisible boundary (Note 3) ICH2 (USB controller 1) 16 contiguous bytes starting on a 16-byte divisible boundary ICH2 (SMBus) 4096 contiguous bytes starting on a Intel 82801BA PCI bridge 4096-byte divisible boundary 96 contiguous bytes starting on a 128-byte divisible boundary LPC47M102 Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only Interrupts The interrupts can be routed through the Advanced Programmable Interrupt Controller (APIC) portion of the ICH2 component. The APIC is supported in Windows† 2000 Server and Windows XP and supports a total of twenty-four interrupts. Table 41. IRQ NMI 0 1 2 3 4 5 6 7 8 9 10 11 Interrupts System Resource I/O channel check Reserved, interval timer Reserved, keyboard buffer full Reserved, cascade interrupt from slave PIC COM2 (Note 1) COM1 (Note 1) MPU-401 FDD0 LPT1 (Note 1) FDD1 Real-time clock Reserved for ICH2 system management bus User available User available continued 88 Intel Server Board S845WD1-E (S845WD1H) Product Guide