Intel X5472 Data Sheet - Page 17

Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the Quad-Core Intel® Xeon® Processor 5400 Series core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor. It is possible to override this setting using software (see the Intel® 64 and IA-32 Architectures Software Developer's Manual). This permits operation at lower frequencies than the processor's tested frequency. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the Intel® 64 and Intel® 64 and IA-32 Architectures Software Developer's Manual. Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. Processor DC specifications for the BCLK[1:0] inputs are provided in Table 2-20. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2-20. The Quad-Core Intel® Xeon® Processor 5400 Series utilizes differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding core frequencies. Table 2-1. Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Multiplier 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 Core Frequency with 400.000 MHz Bus Clock 2.40 GHz 2.80 GHz 3 GHz 3.20 GHz 3.40 GHz 3.60 GHz 3.80 GHz Core Frequency with 333.333 MHz Bus Clock 2 GHz 2.33 GHz 2.50 GHz 2.66 GHz 2.83 GHz 3 GHz 3.16 GHz Core Frequency with 266.666 MHz Bus Clock 1.60 GHz 1.87 GHz 2 GHz 2.13 GHz 2.27 GHz 2.40 GHz 2.53 GHz Notes 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes: 1. Individual processors operate only at or below the frequency marked on the package. 2. Listed frequencies are not necessarily committed production frequencies. 3. For valid processor core frequencies, see Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. 4. The lowest bus ratio supported by the Quad-Core Intel® Xeon® Processor 5400 Series is 1/6. 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT, and are used to select the FSB frequency. Please refer to Table 2-15 for DC specifications. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB agents must operate at the same core and FSB frequency. See the appropriate platform design guidelines for further details. 17