Intel X5472 Data Sheet - Page 73

Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 8) Name BSEL[2:0] COMP[3:0] D[63:0]# Type Description Notes O The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processors, chipset, and clock synthesizer. All FSB agents must operate at the same frequency. For more information about these signals, including termination recommendations, refer to the appropriate platform design guideline. I COMP[3:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines for implementation details. I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit 3 data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to strobes and DBI#. DBI[3:0]# Data Group DSTBN#/DST BP# D[15:0]# 0 D[31:16]# 1 D[47:32]# 2 D[63:48]# 3 DBI# 0 1 2 3 Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. I/O DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate 3 the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0] Assignment to Data Bus Bus Signal Data Bus Signals DBI0# DBI1# DBI2# DBI3# D[15:0]# D[31:16]# D[47:32]# D[63:48]# DBR# DBSY# O DBR# is used only in systems where no debug port connector is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port connector is implemented in the system, DBR# is a noconnect on the Quad-Core Intel® Xeon® Processor 5400 Series package. DBR# is not a processor signal. I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for 3 driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor FSB agents. 73