Intel X5472 Data Sheet - Page 39
AGTL+ FSB Specifications
UPC - 735858201551
View all Intel X5472 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 39 highlights
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-11. VCC Overshoot Example Waveform VID + 0.050 Example Overshoot Waveform VOS Voltage [V] VID - 0.000 2.13.3 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 2-18 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-8 for details on which signals do not include on-die termination. Please refer to Table 2-19 for RTT values. Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END is the reference voltage for the FSB 4X data signals, GTLREF_ADD_MID, and GTLREF_ADD_END is the reference voltage for the FSB 2X address signals and common clock signals. Table 2-19 lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications. 39