Intel X5472 Data Sheet - Page 51

51

Land Listing

4

Land Listing

4.1

Quad-Core Intel® Xeon® Processor 5400 Series

Pin Assignments

This section provides sorted land list in

Table 4-1

and

Table 4-2

.

Table 4-1

is a

listing of all processor lands ordered alphabetically by land name.

Table 4-2

is

a listing of all processor lands ordered by land number.

4.1.1

Land Listing by Land Name

Table 4-1.


(Sheet 1 of 20)

Pin Name

Pin

No.

Signal Buffer

Type

Direction

A03#

M5

Source Sync

Input/Output

A04#

P6

Source Sync

Input/Output

A05#

L5

Source Sync

Input/Output

A06#

L4

Source Sync

Input/Output

A07#

M4

Source Sync

Input/Output

A08#

R4

Source Sync

Input/Output

A09#

T5

Source Sync

Input/Output

A10#

U6

Source Sync

Input/Output

A11#

T4

Source Sync

Input/Output

A12#

U5

Source Sync

Input/Output

A13#

U4

Source Sync

Input/Output

A14#

V5

Source Sync

Input/Output

A15#

V4

Source Sync

Input/Output

A16#

W5

Source Sync

Input/Output

A17#

AB6

Source Sync

Input/Output

A18#

W6

Source Sync

Input/Output

A19#

Y6

Source Sync

Input/Output

A20#

Y4

Source Sync

Input/Output

A20M#

K3

CMOS ASync

Input

A21#

AA4

Source Sync

Input/Output

A22#

AD6

Source Sync

Input/Output

A23#

AA5

Source Sync

Input/Output

A24#

AB5

Source Sync

Input/Output

A25#

AC5

Source Sync

Input/Output

A26#

AB4

Source Sync

Input/Output

A27#

AF5

Source Sync

Input/Output

A28#

AF4

Source Sync

Input/Output

A29#

AG6

Source Sync

Input/Output

A30#

AG4

Source Sync

Input/Output

A31#

AG5

Source Sync

Input/Output

A32#

AH4

Source Sync

Input/Output

A33#

AH5

Source Sync

Input/Output

A34#

AJ5

Source Sync

Input/Output

A35#

AJ6

Source Sync

Input/Output

A36#

N4

Source Sync

Input/Output

A37#

P5

Source Sync

Input/Output

ADS#

D2

Common Clk

Input/Output

ADSTB0#

R6

Source Sync

Input/Output

ADSTB1#

AD5

Source Sync

Input/Output

AP0#

U2

Common Clk

Input/Output

AP1#

U3

Common Clk

Input/Output

BCLK0

F28

Clk

Input

BCLK1

G28

Clk

Input

BINIT#

AD3

Common Clk

Input/Output

BNR#

C2

Common Clk

Input/Output

BPM0#

AJ2

Common Clk

Input/Output

BPM1#

AJ1

Common Clk

Output

BPM2#

AD2

Common Clk

Output

BPM3#

AG2

Common Clk

Input/Output

BPM4#

AF2

Common Clk

Output

BPM5#

AG3

Common Clk

Input/Output

BPMb0#

G1

Common Clk

Input/Output

BPMb1#

C9

Common Clk

Output

BPMb2#

G4

Common Clk

Output

BPMb3#

G3

Common Clk

Input/Output

BPRI#

G8

Common Clk

Input

BR0#

F3

Common Clk

Input/Output

BR1#

H5

Common Clk

Input

Table 4-1.


(Sheet 2 of 20)

Pin Name

Pin

No.

Signal Buffer

Type

Direction

Section	Page
Quad-Core Intel® Xeon® Processor 5400 Series	1
1 Introduction	9
1.1 Terminology	10
1.2 State of Data	13
1.3 References	13
2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	16
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	17
2.4.2 PLL Power Supply	18
2.5 Voltage Identification (VID)	18
2.6 Reserved, Unused, and Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	38
2.13.3 Die Voltage Validation	39
2.14 AGTL+ FSB Specifications	39
3 Mechanical Specifications	43
3.1 Package Mechanical Drawings	43
3.2 Processor Component Keepout Zones	47
3.3 Package Loading Specifications	47
3.4 Package Handling Guidelines	48
3.5 Package Insertion Specifications	48
3.6 Processor Mass Specifications	48
3.7 Processor Materials	48
3.8 Processor Markings	48
3.9 Processor Land Coordinates	49
4 Land Listing	51
4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments	51
4.1.1 Land Listing by Land Name	51
4.1.2 Land Listing by Land Number	61
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	90
6.2 Processor Thermal Features	90
6.2.1 Intel® Thermal Monitor Features	90
6.2.2 On-Demand Mode	92
6.2.3 PROCHOT# Signal	93
6.2.4 FORCEPR# Signal	93
6.2.5 THERMTRIP# Signal	94
6.3 Platform Environment Control Interface (PECI)	94
6.3.1 Introduction	94
6.3.2 PECI Specifications	96
7 Features	97
7.1 Power-On Configuration Options	97
7.2 Clock Control and Low Power States	97
7.2.1 Normal State	98
7.2.2 HALT or Extended HALT State	98
7.2.3 Stop-Grant State	100
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	101
7.3 Enhanced Intel SpeedStep® Technology	101
8 Boxed Processor Specifications	103
8.1 Introduction	103
8.2 Mechanical Specifications	105
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	105
8.2.2 Boxed Processor Heat Sink Weight	113
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	113
8.3 Electrical Requirements	113
8.3.1 Fan Power Supply (Active CEK)	113
8.3.2 Boxed Processor Cooling Requirements	114
8.4 Boxed Processor Contents	115
9 Debug Tools Specifications	117
9.1 Debug Port System Requirements	117
9.2 Target System Implementation	117
9.2.1 System Implementation	117
9.3 Logic Analyzer Interface (LAI)	117
9.3.1 Mechanical Considerations	118

Intel X5472 Data Sheet - Page 51

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