Intel X5472 Data Sheet - Page 40

Table 2-19., AGTL+ Bus Voltage Definitions, Table 2-20., FSB Differential BCLK Specifications

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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details. Table 2-19. AGTL+ Bus Voltage Definitions Symbol Parameter GTLREF_DATA_MID, Data Bus Reference GTLREF_DATA_END Voltage GTLREF_ADD_MID, Address Bus Reference GTLREF_ADD_END Voltage RTT Termination Resistance (pull up) COMP COMP Resistance Min 0.98 * 0.667 * VTT 0.98 * 0.667 * VTT 45 49.4 Typ 0.667 * VTT 0.667 * VTT 50 Max 1.02*0.667 * VTT 1.02*0.667 * VTT 55 49.9 50.4 Units V V Ω Ω Notes1 2, 3 2, 3 4 5 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VTT. 3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from VTT on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance. Refer to the appropriate platform design guidelines for implementation details. The VTT referred to in these specifications is the instantaneous VTT. 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VTT. RTT is connected to VTT on die. Refer to processor I/O Buffer Models for I/V characteristics. 5. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. Table 2-20. FSB Differential BCLK Specifications Symbol VL VH VCROSS(abs) VCROSS(rel) Δ VCROSS VOS VUS VRBM VTR ILI ERRefclk-diffRrise ERRefclk-diff-Fall Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Min -0.150 0.660 0.250 Relative Crossing Point Range of Crossing Points Overshoot Undershoot Ringback Margin Threshold Region Input Leakage Current Differential Rising and falling edge rates 0.250 + 0.5 * (VHavg 0.700) N/A N/A -0.300 0.200 VCROSS 0.100 N/A 0.6 Typ 0.0 0.710 0.350 Max 0.150 0.850 0.550 Unit V V V N/A 0.550 + V 0.5 * (VHavg 0.700) N/A 0.140 V N/A 1.150 V N/A N/A V N/A N/A V N/A VCROSS V + 0.100 N/A ± 100 μA 4 V/ns Figure 2-13 2-13 2-13, 2-14 2-13, 2-14 2-13, 2-14 2-13 2-13 2-13 2-13 2-15 Notes1 2,9 3,8,9,11 4 5 6 7 10 12 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 40

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Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
40
The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard
using high precision voltage divider circuits. Refer to the appropriate platform design
guidelines for implementation details.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V
TT
.
3.
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V
TT
on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account
for this resistor tolerance. Refer to the appropriate platform design guidelines for implementation details.
The V
TT
referred to in these specifications is the instantaneous V
TT
.
4.
R
TT
is the on-die termination resistance measured at V
OL
of the AGTL+ output driver. Measured at
0.31*V
TT
. R
TT
is connected to V
TT
on die. Refer to processor I/O Buffer Models for I/V characteristics.
5.
COMP resistance must be provided on the system board with 1% resistors. See the applicable platform
design guide for implementation details.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to
the falling edge of BCLK1.
3.
V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
4.
Overshoot is defined as the absolute value of the maximum voltage.
5.
Undershoot is defined as the absolute value of the minimum voltage.
6.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
Table 2-19.
AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF_DATA_MID,
GTLREF_DATA_END
Data Bus Reference
Voltage
0.98 *
0.667 * V
TT
0.667 *
V
TT
1.02*0.667
* V
TT
V
2, 3
GTLREF_ADD_MID,
GTLREF_ADD_END
Address Bus Reference
Voltage
0.98 *
0.667 * V
TT
0.667 *
V
TT
1.02*0.667
* V
TT
V
2, 3
R
TT
Termination
Resistance (pull up)
45
50
55
Ω
4
COMP
COMP Resistance
49.4
49.9
50.4
Ω
5
Table 2-20.
FSB Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
1
V
L
Input Low Voltage
-0.150
0.0
0.150
V
2-13
V
H
Input High Voltage
0.660
0.710
0.850
V
2-13
V
CROSS(abs)
Absolute Crossing Point
0.250
0.350
0.550
V
2-13,
2-14
2,9
V
CROSS(rel)
Relative Crossing Point
0.250 +
0.5 *
(V
Havg
-
0.700)
N/A
0.550 +
0.5 *
(V
Havg
-
0.700)
V
2-13,
2-14
3,8,9,11
Δ
VCROSS
Range of Crossing
Points
N/A
N/A
0.140
V
2-13,
2-14
V
OS
Overshoot
N/A
N/A
1.150
V
2-13
4
V
US
Undershoot
-0.300
N/A
N/A
V
2-13
5
V
RBM
Ringback Margin
0.200
N/A
N/A
V
2-13
6
V
TR
Threshold Region
V
CROSS
-
0.100
N/A
V
CROSS
+ 0.100
V
2-13
7
I
LI
Input Leakage Current
N/A
N/A
± 100
μ
A
10
ERRefclk-diffRrise
ERRefclk-diff-Fall
Differential Rising and
falling edge rates
0.6
4
V/ns
2-15
12