ASRock N100M Software/BIOS Setup Guide - Page 28

RAS# Active Time tRAS

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DRAM Reference Clock Allows you to configure DRAM Reference Clock. Select [Auto] for optimized settings. Configuration options: [Auto] [100MHz] [133MHz] DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Gear Mode Allows you to select the DRAM Gear Mode. High gear is good for high frequency. Configuration options: [Auto] [Gear 2] [Gear 4] Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Secondary Timing Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. 24

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DRAM Reference Clock
Allows you to configure DRAM Reference Clock. Select [Auto] for optimized settings.
Configuration options: [Auto] [100MHz] [133MHz]
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted and
assign the appropriate frequency automatically.
DRAM Gear Mode
Allows you to select the DRAM Gear Mode. High gear is good for high frequency.
Configuration options: [Auto] [Gear 2] [Gear 4]
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
RAS# to CAS# Delay : °e number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge (tRP)
°e number of clock cycles required between the issuing of the precharge command and
opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
°e delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
°e amount of delay that must elapse aſter the completion of a valid write operation, before
an active bank can be precharged.