Brother International HL-1070 Service Manual - Page 21

XIO interrupt RS-100M or MIO interrupt, LSB EMPTY for VDO FIFO

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1.3.2 ASIC The ASIC is composed of a Cell Based IC that contains the following functional blocks. (1) Oscillator circuit Generates the main clock for the CPU. (2) Address decoder Generates the CS signal for each device. (3) DRAM control Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the refresh processing (CAS before RAS self-refreshing method). (4) Interrupt control Interrupt levels: Priority High Low 10 Reserve interrupt 1 (for debug) 9 Watch Dog Timer 8 LSB EMPTY (for VDO FIFO) 7 Timer 1 6 USB 5 XIO interrupt (RS-100M) or MIO interrupt 4 BD (for engine check) 3 Reserve interrupt 2 2 CDCC 1 Timer 2 Note:  All the interrupts can be masked.  The priority of level 7, 6, and 5 are changeable from the program. (5) Timers The following timers are included: Timer 1 Timer 2 Timer 3 32-bit timer 32-bit timer Watch-dog timer (6) FIFO A 10Kbit FIFO is included. Data for one raster is transferred from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle is 10.43mhz. II-5

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II-5
1.3.2
ASIC
The ASIC is composed of a Cell Based IC that contains the following functional blocks.
(1)
Oscillator circuit
Generates the main clock for the CPU.
(2)
Address decoder
Generates the CS signal for each device.
(3)
DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the
refresh processing (CAS before RAS self-refreshing method).
(4)
Interrupt control
Interrupt levels:
Priority
High
10
Reserve interrupt 1 (for debug)
9
Watch Dog Timer
8
LSB EMPTY (for VDO FIFO)
7
Timer 1
6
USB
5
XIO interrupt (RS-100M) or MIO interrupt
4
BD (for engine check)
3
Reserve interrupt 2
2
CDCC
Low
1
Timer 2
Note:
All the interrupts can be masked.
The priority of level 7, 6, and 5 are changeable from the program.
(5)
Timers
The following timers are included:
Timer 1
32-bit timer
Timer 2
32-bit timer
Timer 3
Watch-dog timer
(6)
FIFO
A 10Kbit FIFO is included. Data for one raster is transferred from the RAM to the
FIFO by DMA transmission and is output as serial video data. The data cycle is
10.43mhz.