Brother International HL 760 Service Manual - Page 13

Brother International HL 760 - B/W Laser Printer Manual

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1.3.2 ASIC The ASIC is composed of Cell Based IC and has the following function blocks. (1) Oscillator circuit Generates the main clock for the CPU by dividing the source clock frequency into two. (2) Address Generator It forms address bass by ratchetting the AD bass with the ALE signal. (3) Address decoder Generates the CS for each device. (4) DRAM control Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls refresh processing (CAS before RAS self-refreshing method). (5) Interrupt control Interrupt levels: Priority High 9 TIMER 3 (Watch Dog) 8 MONITOR 7 FIFO 6 EXINT 5 TIMER1 4 BD 3 Spare 2 CDCC / BOISE / DATA EXTENTION Low 1 TIMER 2 (6) Timers All of the breaking can mask. The following timers are incorporated: Timer 1 Timer 2 Timer 3 16-bit timer 10-bit timer Watch-dog timer (7) FIFO A 10kbit FIFO is incorporated. Data for one raster is transfered from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle is 6.13 MHz. II - 4

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1.3.2
ASIC
The
ASIC
is
composed
of
Cell
Based
IC
and
has
the
following
function
blocks.
(1)
Oscillator
circuit
Generates
the
main
clock
for
the
CPU
by
dividing
the
source
clock
frequency
into
two.
(2)
Address
Generator
It
forms
address
bass
by
ratchetting
the
AD
bass
with
the
ALE
signal.
(3)
Address
decoder
Generates
the
CS
for
each
device.
(4)
DRAM
control
Generates
the
RAS,
CAS,
WE,
OE
and
MA
signals
for
the
DRAM
and
controls
refresh
processing
(CAS
before
RAS
self
-refreshing
method).
(5)
Interrupt
control
Interrupt
levels:
Priority
High
9
TIMER
3
(Watch
Dog)
8
MONITOR
7
FIFO
6
EXINT
5
TIMER1
4
BD
3
Spare
2
CDCC
/
BOISE
/
DATA
EXTENTION
Low
1
TIMER
2
All
of
the
breaking
can
mask.
(6)
Timers
The
following
timers are
incorporated:
Timer
1
Timer
2
Timer
3
16
-bit
timer
10
-bit
timer
Watch
-dog
timer
(7)
FIFO
A
10kbit
FIFO
is
incorporated.
Data
for
one
raster
is
transfered
from
the
RAM
to
the
FIFO
by
DMA
transmission
and
is
output
as
serial
video
data.
The
data
cycle
is
6.13
MHz.
II
-
4