Compaq DC7600 HP Compaq dx 7200 and dc7600 Personal Computers, Technical Refer - Page 52

Processor/Memory Subsystem The SPD address map is shown in Table 3-2. Byte 0 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Table 3-2 SPD Address Map (SDRAM DIMM) Description Notes Byte Description No. of Bytes Written Into EEPROM [1] 25 Min. CLK Cycle Time at CL X-2 Total Bytes (#) In EEPROM [2] 26 Max. Acc. Time From CLK @ CL X-2 Memory Type 27 Min. Row Prechge. Time No. of Row Addresses On DIMM [3] 28 Min. Row Active to Delay No. of Column Addresses On DIMM 29 Min. RAS to CAS Delay No. of Module Banks On DIMM 30-31 Reserved Data Width of Module 32-61 Superset Data Voltage Interface Standard of DIMM 62 SPD Revision Cycletime @ Max CAS Latency (CL) [4] 63 Checksum Bytes 0-62 Access From Clock [4] 64-71 JEP-106E ID Code Config. Type (Parity, Nonparity...) 72 DIMM OEM Location Refresh Rate/Type [4][5] 73-90 OEM's Part Number Width, Primary DRAM 91-92 OEM's Rev. Code Error Checking Data Width Min. Clock Delay 93-94 [6] 95-98 Manufacture Date OEM's Assembly S/N Burst Lengths Supported No. of Banks For Each Mem. Device 99125 [4] 126 OEM Specific Data Intel frequency check CAS Latencies Supported [4] 127 Reserved CS# Latency [4] 128 - 131 Compaq header "CPQ1" Write Latency [4] 132 Header checksum DIMM Attributes 133 - 145 Unit serial number Memory Device Attributes 146 DIMM ID Min. CLK Cycle Time at CL X-1 [7] 147 Checksum Max. Acc. Time From CLK @ CL X-1 [7] 148 Reserved Notes [7] [7] [7] [7] [7] [7] [7] [8] [8] [8] [8] [8] [8] [8] [9] [9] [9][10] [9][11] [9] [9] NOTES: [1] Programmed as 128 bytes by the DIMM OEM [2] Must be programmed to 256 bytes. [3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be re-sent as highest order CAS# address. [4] Refer to memory manufacturer's datasheet [5] MSb is Self Refresh flag. If set (1), assembly supports self refresh. [6] Back-to-back random column addresses. [7] Field format proposed to JEDEC but not defined as standard at publication time. [8] Field specified as optional by JEDEC but required by this system. [9] HP usage. This system requires that the DIMM EEPROM have this space available for reads/writes. [10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is invalid. Can also be used to indicate s/n mismatch and flag system adminstrator of possible system Tampering. [11]Contains the socket # of the module (first module is "1"). Intended as backup identifier (refer to note [10]). 3-6 www.hp.com Technical Reference Guide