Compaq DC7600 HP Compaq dx 7200 and dc7600 Personal Computers, Technical Refer - Page 72

System Support The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The refresh rate is 128 refresh cycles in 2.038 ms. DMA Controller Registers Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a set of registers for each DMA controller. Table 4-11. DMA Controller Registers Register Controller 1 Status 008h Command 008h Mode 00Bh Write Single Mask Bit 00Ah Write All Mask Bits 00Fh Software DRQx Request 009h Base and Current Address-Ch 0 000h Current Address-Ch 0 000h Base and Current Word Count-Ch 0 001h Current Word Count-Ch 0 001h Base and Current Address-Ch 1 002h Current Address-Ch 1 002h Base and Current Word Count-Ch 1 003h Current Word Count-Ch 1 003h Base and Current Address-Ch 2 004h Current Address-Ch 2 004h Base and Current Word Count-Ch 2 005h Current Word Count-Ch 2 005h Base and Current Address-Ch 3 006h Current Address-Ch 3 006h Base and Current Word Count-Ch 3 007h Current Word Count-Ch 3 007h Temporary (Command) 00Dh Reset Pointer Flip-Flop (Command) 00Ch Master Reset (Command) 00Dh Reset Mask Register (Command) 00Eh Controller 2 0D0h 0D0h 0D6h 0D4h 0DEh 0D2h 0C0h 0C0h 0C2h 0C2h 0C4h 0C4h 0C6h 0C6h 0C8h 0C8h 0CAh 0CAh 0CCh 0CCh 0CEh 0CEh 0DAh 0D8h 0DAh 0DCh R/W R W W W W W W R W R W R W R W R W R W R W R R W W W 4-18 www.hp.com Technical Reference Guide