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Hitachi HDT725025VLA380 Specifications - Page 41

Interface logic signal levels pata model, Signal definition SATA model - deskstar sata driver

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6.4 Interface logic signal levels (pata model) The interface logic signals have the following electrical specification: Inputs Outputs: Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 2.0 V min 0.8 V max. 2.4 V min. 0.5 V max. 6.5 Signal definition (SATA model) SATA has receivers and drivers to be connected to Tx+/- and Rx +/- Serial data signal. defines the signal names of I/O connector pin and signal name. No. Plug Connector pin definition Signal I/O S1 GND 2nd mate Gnd S2 A+ Differential signal A from Phy RX+ Input S3 A- RX- Input Signal S4 Gnd 2nd mate Gnd S5 B- Differential signal B from Phy TX- Output S6 B+ TX+ Output S7 Gnd 2nd mate Gnd Key and spacing separate signal and power segments P1 V33 3.3V power 3.3V P2 V33 3.3V power 3.3V P3 V33 3.3V power, pre-charge, 2nd Mate 3.3V P4 Gnd 1st mate Gnd P5 Gnd 2nd mate Gnd P6 Gnd 2nd mate Gnd P7 V5 5V power,pre-charge,2nd Mate 5V P8 V5 5V power 5V Power P9 V5 5V power 5V P10 Gnd 2nd mate Gnd P11 Reserved This pin can be used for LED activity and staggered Spin up. It is controlled by firmware. Reserve P12 Gnd 1st mate Gnd P13 V12 12V power,pre-chage,2nd mate V12 P14 V12 12V power V12 P15 V12 12V power V12 6.5.1 TX+ / TX- These signal are the outbound high-speed differrential signals that are connected to the serial ATA cable. Deskstar T7K500 Hard Disk Drive Specification 27

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	27
4.3 World Wide Name Assignment	27
4.4 Drive organization	27
4.4.1 Drive format	27
4.4.2 Cylinder allocation	28
4.5 Performance characteristics	29
4.5.1 Command overhead	29
4.5.2 Mechanical positioning	29
4.5.3 Drive ready time	31
4.5.4 Operating modes	31
5.0 Defect flagging strategy	33
6.0 Electrical interface specification	35
6.1 Connector location	35
6.1.1 4 pin DC power connector	36
6.1.2 AT signal connector	36
6.2 Signal definitions (PATA model)	37
6.3 Signal descriptions	38
6.4 Interface logic signal levels (pata model)	41
6.5 Signal definition (SATA model)	41
6.5.1 TX+ / TX-	41
6.5.2 RX+ / RX-	42
6.5.3 Out of band signaling (SATA model)	42
6.6 Reset timings	43
6.7 PIO timings	44
6.7.1 Write DRQ interval time	44
6.7.2 Read DRQ interval time	44
6.8 Multi-word DMA timings	45
6.9 Ultra DMA timings	46
6.9.1 Initiating Read DMA	46
6.9.2 Host Pausing Read DMA	47
6.9.3 Host Terminating Read DMA	48
6.9.4 Device Terminating Read DMA	49
6.9.5 Initiating Write DMA	50
6.9.6 Device Pausing Write DMA	51
6.9.7 Device Terminating Write DMA	52
6.9.8 Host Terminating Write DMA	53
6.10 Addressing of registers	54
6.10.1 Cabling	54
7.0 Specification	57
7.1 Jumper settings	57
7.1.1 Jumper pin location	57
7.1.2 Jumper pin identification	57
7.1.3 Jumper pin assignment	57
7.1.4 Jumper positions	59
7.2 Environment	63
7.2.1 Temperature and humidity	63
7.2.2 Corrosion test	64
7.3 DC power requirements	64
7.3.1 Input voltage	65
7.3.2 Power supply current (typical)	66
7.3.3 Power supply generated ripple at drive power connector	67
7.4 Reliability	69
7.4.1 Data integrity	69
7.4.2 Cable noise interference	69
7.4.3 Start/stop cycles	69
7.4.4 Preventitive Maintenance	69
7.4.5 Data reliability	69
7.4.6 Required power-off sequence	69
7.5 Mechanical specifications	70
7.5.1 Physical dimensions and weight	70
7.5.2 Mounting hole locations	72
7.5.3 Connector locations	73
7.5.4 Drive mounting	74
7.5.5 Heads unload and actuator lock	74
7.6 Vibration and shock	75
7.6.1 Operating vibration	75
7.6.2 Nonoperating vibration	75
7.6.3 Operating shock	76
7.6.4 Nonoperating shock	76
7.6.5 Nonoperating rotational shock	76
7.7 Acoustics	77
7.8 Identification labels	77
7.9 Safety	78
7.9.1 UL and CSA approval	78
7.9.2 German safety mark	78
7.9.3 Flammability	78
7.9.4 Safe handling	78
7.9.5 Environment	78
7.9.6 Secondary circuit protection	78
7.10 Electromagnetic compatibility	79
7.10.1 CE Mark	79
7.10.2 C-TICK mark	79
7.10.3 BSMI mark	79
7.10.4 MIC Mark	79
7.11 Packaging	79
7.11.1 Substance restriction requirements	79
8.0 General	81
8.1 Introduction	81
8.2 Terminology	81
8.3 Deviations from standard	81
9.0 Registers	83
9.1 Register set	83
9.2 Alternate Status Register	84
9.3 Command Register	84
9.4 Cylinder High Register	84
9.5 Cylinder Low Register	84
9.6 Data Register	85
9.7 Device Control Register	85
9.8 Drive Address Register	86
9.9 Device/Head Register	86
9.10 Error Register	87
9.11 Features Register	87
9.12 Sector Count Register	87
9.13 Sector Number Register	88
9.14 Status Register	88
10.0 General operation	91
10.1 Reset response	91
10.2 Register initialization	92
10.3 Diagnostic and Reset considerations	93
10.4 Sector Addressing Mode	94
10.4.1 Logical CHS addressing mode	94
10.4.2 LBA addressing mode	94
10.5 Power management features	95
10.5.1 Power mode	95
10.5.2 Power management commands	95
10.5.3 Standby timer	95
10.5.4 Interface capability for power modes	96
10.6 S.M.A.R.T. Function	97
10.6.1 Attributes	97
10.6.2 Attribute values	97
10.6.3 Attribute thresholds	97
10.6.4 Threshold exceeded condition	97
10.6.5 S.M.A.R.T. commands	97
10.6.6 Off-line read scanning	97
10.6.7 Error log	98
10.6.8 Self-test	98
10.7 Security Mode Feature Set	99
10.7.1 Security mode	99
10.7.2 Security level	99
10.7.3 Passwords	100
10.7.4 Operation example	100
10.7.5 Command table	104
10.8 Host Protected Area Feature	106
10.8.1 Example for operation (In LBA Mode)	106
10.8.2 Security extensions	107
10.9 Seek overlap	108
10.10 Write cache function	109
10.11 Reassign function	110
10.11.1 Auto Reassign function	110
10.12 Power-Up in Standby feature set	111
10.13 Advanced Power Management feature set (APM)	112
10.14 Automatic Acoustic Management feature set (AAM)	113
10.15 Address Offset Feature	114
10.15.1 Enable/Disable Address Offset Mode	114
10.15.2 Identify Device Data	115
10.15.3 Exceptions in Address Offset Mode	115
10.16 48-bit Address Feature Set	116
10.17 Streaming feature Set	116
10.17.1 Streaming commands	117
10.17.2 Urgent bit	117
10.17.3 Flush to Disk bit	117
10.17.4 Not Sequential bit	117
10.17.5 Read Continuous bit	118
10.17.6 Write Continuous bit	118
10.17.7 Handle Streaming Error bit	118
10.17.8 Streaming Logs	118
10.18 SCT Command Transport Feature Set	118
10.18.1 SCT Command Protocol	119
10.18.2 SCT Command Set	125
11.0 Command protocol	137
11.1 PIO Data In commands	137
11.2 PIO Data Out Commands	138
11.3 Non-data commands	140
11.4 DMA commands	141
12.0 Command descriptions	143
12.1 Check Power Mode (E5h/98h)	148
12.2 Configure Stream (51h)	149
12.3 Device Configuration Overlay (B1h)	151
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h)	151
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	151
12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	152
12.3.4 DEVICE CONFIGURATION SET (subcommand C3h)	152
12.4 Download Microcode (92h)	155
12.5 Execute Device Diagnostic (90h)	156
12.6 Flush Cache (E7h)	157
12.7 Flush Cache Ext (EAh)	158
12.8 Format Track (50h)	159
12.9 Format Unit (F7h)	161
12.10 Identify Device (ECh)	162
12.11 Idle (E3h/97h)	173
12.12 Idle Immediate (E1h/95h)	174
12.13 Initialize Device Parameters (91h)	175
12.14 Read Buffer (E4h)	176
12.15 Read DMA (C8h/C9h)	177
12.16 Read DMA Ext (25h)	179
12.17 Read Log Ext (2Fh)	181
12.17.1 General Purpose Log Directory	183
12.17.2 Extended Comprehensive SMART Error Log	184
12.17.3 Extended Self-test log sector	186
12.17.4 Read Stream Error Log	187
12.17.5 Write Stream Error Log	189
12.17.6 Streaming Performance Log	190
12.18 Read Long (22h/23h)	192
12.19 Read Multiple (C4h)	194
12.20 Read Multiple Ext (29h)	195
12.21 Read Native Max ADDRESS (F8h)	197
12.22 Read Native Max Address Ext (27h)	198
12.23 Read Sectors (20h/21h)	199
12.24 Read Sector(s) Ext (24h)	201
12.25 Read Stream DMA (2Ah)	203
12.26 Read Stream PIO (2Bh)	207
12.27 Read Verify Sectors (40h/41h)	210
12.28 Read Verify Sectors Ext (42h)	212
12.29 Recalibrate (1xh)	214
12.30 Security Disable Password (F6h)	215
12.31 Security Erase Prepare	216
12.32 Security Erase Unit (F4h)	217
12.33 Security Freeze Lock (F5h)	219
12.34 Security Set Password (F1h)	220
12.35 Security Unlock (F2h)	222
12.36 Seek (7xh)	224
12.37 Set Features (EFh)	225
12.37.1 Set Transfer mode	226
12.37.2 Write Cache	226
12.37.3 Advanced Power Management	226
12.37.4 Automatic Acoustic Management	228
12.38 Set Max ADDRESS (F9h)	229
12.38.1 Set Max Set Password (Feature=01h)	231
12.38.2 Set Max Lock (Feature=02h)	232
12.38.3 Set Max Unlock (Feature = 03h)	233
12.38.4 Set Max Freeze Lock (Feature = 04h)	234
12.39 Set Max Address Ext (37h)	235
12.40 Set Multiple (C6h)	237
12.41 Sleep (E6h/99h)	238
12.42 S.M.A.R.T. Function Set (B0h)	239
12.42.1 S.M.A.R.T. Function Subcommands	240
12.42.2 Device Attribute Data Structure	244
12.42.3 Device Attribute Thresholds data structure	247
12.42.4 S.M.A.R.T. Log Directory	249
12.42.5 S.M.A.R.T. summary error log sector	249
12.42.6 Self-test log data structure	251
12.42.7 Selective self-test log data structure	252
12.42.8 Error reporting	253
12.43 Standby (E2h/96h)	255
12.44 Standby Immediate (E0h/94h)	257
12.45 Write Buffer (E8h)	258
12.46 Write DMA (CAh/CBh)	259
12.47 Write DMA Ext (35h)	261
12.48 Write DMA FUA Ext (3Dh)	263
12.49 Write Log Ext (3Fh)	265
12.50 Write Long (32h/33h)	266
12.51 Write Multiple (C5h)	268
12.52 Write Multiple Ext (39h)	270
12.53 Writer Multiple FUA Ext (CEh)	272
12.54 Write Sectors (30h/31h)	274
12.55 Write Sector(s) Ext (34h)	276
12.56 Write Stream DMA (3Ah)	278
12.57 Write Stream PIO (3Bh)	280

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Deskstar T7K500 Hard Disk Drive Specification

6.4

Interface logic signal levels (pata model)

The interface logic signals have the following electrical specification:

6.5

Signal definition (SATA model)

SATA has receivers and drivers to be connected to Tx+/- and Rx +/- Serial data signal.

defines the signal names of I/O connector pin and signal name.

6.5.1

TX+ / TX-

These signal are the outbound high-speed differrential signals that are connected to the serial ATA cable.

Inputs

Input High Voltage

Input Low Voltage

2.0 V min

0.8 V max.

Outputs:

Output High Voltage

Output Low Voltage

2.4 V min.

0.5 V max.

No.

Plug Connector pin definition

Signal

I/O

GND

2nd mate

Gnd

A+

Differential signal A from Phy

RX+

Input

A-

RX-

Input

Signal

Gnd

2nd mate

Gnd

B-

Differential signal B from Phy

TX-

Output

B+

TX+

Output

Gnd

2nd mate

Gnd

Key and spacing separate signal and power segments

V33

3.3V power

3.3V

V33

3.3V power

3.3V

V33

3.3V power, pre-charge, 2nd Mate

3.3V

Gnd

1st mate

Gnd

2nd mate

Gnd

2nd mate

Gnd

5V power,pre-charge,2nd Mate

5V power

Power

5V power

P10

Gnd

2nd mate

Gnd

P11

Reserved

This pin can be used for LED activity and staggered

Spin up. It is controlled by firmware.

Reserve

P12

Gnd

1st mate

Gnd

P13

V12

12V power,pre-chage,2nd mate

V12

P14

V12

12V power

V12

P15

V12

12V power

V12