Hitachi HDT725025VLA380 Specifications - Page 45
Multi-word DMA timings
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• In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs • In the event that a host reads the status register after or both before and after the sector or block transfer, the DRQ interval is 11.5 µs 6.8 Multi-word DMA timings The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description. Table 18: Multiword DMA cycle timing chart CS0-/CS1- tM DMARQ tLR/tLW DMACKDIOR-/DIOWREAD DATA WRITE DATA t0 tI tD tKR/tKW tE tG tF tG tH tN tJ tZ Table 19: Multiword DMA cycle timings t0 tD tE tF tG tH tI tJ tKR/tKW tLR/tLW tM tN tZ PARAMETER DESCRIPTION Cycle time DIOR-/DIOW- asserted pulse width DIOR- data access DIOR- data hold DIOR-/DIOW- data setup DIOW- data hold DMACK- to -DIOR-/DIOW- setup DIOR-/DIOW- to DMACK- hold DIOR-/DIOW- negated pulse width DIOR-/DIOW- to DMARQ- delay CS (1:0) valid to DIOR-/DIOWCS (1:0) DMACK- to read data released MIN (ns) 120 70 - 5 20 10 0 5 25 - 25 10 - MAX (ns) - - 50 35 25 Deskstar T7K500 Hard Disk Drive Specification 31