IBM 86884RX Installation Guide - Page 25

Feature Issue ports on-board registers Integer units Branch units Floating point units SIMD units Load and store units Itanium 9 328 3 3 2 2 2 (total) Itanium 2 "McKinley" 11 328 6 3 2 1 2 load and 2 store Itanium 2 "Madison" 11 328 6 3 2 1 2 load and 2 store The Itanium 2 processor has three levels of cache, all of which are on the processor die: Level 3 cache is equivalent to L2 cache on the Pentium III Xeon, or the L3 cache on the Pentium Xeon MP processor. Itanium 2 processors in the x450 models contain either 3, 4 or 6 MB of L3 cache. Unlike the design of the original Itanium processor, this L3 cache is now on the processor die, greatly improving performance, up or 2 times greater than that of the original Itanium. Level 2 cache is equivalent to L1 cache on the Pentium III Xeon and is 256 KB in size. A new level 1 cache, 32 KB in size, is "closest" to the processor and is used to store micro-operations (that is, decoded executable machine instructions) and serves those to the processor at rated speed. This additional level of cache saves decode time on cache hits. The x450 also implements a Level 4 cache as described in 1.6, "IBM XceL4 Server Accelerator Cache" on page 17. Intel has also introduced a number of features associated with its Itanium micro-architecture. These are available in the x450, including: 400 MHz frontside bus The Pentium III Xeon processor had a 100 MHz frontside bus that equated to a burst throughput of 800 MBps. With protocols such as TCP/IP, this had been shown to be a bottleneck in high-throughput situations. The Itanium 2 processor improves on this by using a single 200 MHz clock and using both edges of each clock to transmit data. This is shown in Figure 1-6 on page 12. Chapter 1. Technical description 11