IBM 86884RX Installation Guide - Page 31

IBM XceL4 Server Accelerator Cache, 1.7 System memory, Active Memory

Page 31 highlights

1.6 IBM XceL4 Server Accelerator Cache Integrated into the processor-board assembly is 64 MB of Level 4 cache, which is shown in Figure 1-1 on page 4. This XceL4 Server Accelerator Cache provides the necessary extra level of cache to maximize CPU throughput by reducing the need for main memory access under demanding workloads, resulting in an overall enhancement to system performance. Cache memory is two-way interleaved 200 MHz DDR memory and is faster than the main memory because it is directly connected to the memory controller and does not have additional latency associated with the large fan-out necessary to support the 28 DIMM slots. Since the data interface to the controller is 400 MHz, peak bandwidth for the XceL4 cache is 6.4 GBps. 1.7 System memory The x450 has 1 GB or 2 GB of RAM standard, depending on the model. Memory packaging is PC2100 ECC DDR SDRAM DIMMs, and standard memory is either two or four 512 MB DIMMs. Memory options are 512 MB, 1 GB, or 2 GB DIMMs. There are a total of 28 DIMM sockets (two ports of 14). All 28 DIMM sockets can be used to install DIMMs, with the exception of the 2 GB DIMM option. If 2 GB DIMMs are installed, the total number of DIMM sockets that can be used is limited to 20. A maximum of 40 GB of system memory is supported by populating 20 DIMM sockets each with a 2 GB DIMM. DIMMs must be installed in matched pairs, since the DIMMs are two-way interleaved. However, if memory is installed in matched fours (a matched pair in each port), the system automatically detects this and will enable four-way interleaving. With this, memory access is performed simultaneously from both ports (two separate paths into the memory controller as shown in Figure 1-1 on page 4), leading to improved memory performance. See 3.1.2, "Memory" on page 41 for a further discussion of how memory is implemented in the x450 and what you should consider before an x450 installation. There are a number of advanced features implemented in the x450 memory subsystem, collectively known as Active Memory: Restriction: The ability to hot-add or hot-replace memory is not available in the x450. Chapter 1. Technical description 17

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160

Chapter 1. Technical description
17
1.6
IBM XceL4 Server Accelerator Cache
Integrated into the processor-board assembly is 64 MB of Level 4 cache, which is
shown in Figure 1-1 on page 4. This XceL4 Server Accelerator Cache provides
the necessary extra level of cache to maximize CPU throughput by reducing the
need for main memory access under demanding workloads, resulting in an
overall enhancement to system performance.
Cache memory is two-way interleaved 200 MHz DDR memory and is faster than
the main memory because it is directly connected to the memory controller and
does not have additional latency associated with the large fan-out necessary to
support the 28 DIMM slots. Since the data interface to the controller is 400 MHz,
peak bandwidth for the XceL4 cache is 6.4 GBps.
1.7
System memory
The x450 has 1 GB or 2 GB of RAM standard, depending on the model. Memory
packaging is PC2100 ECC DDR SDRAM DIMMs, and standard memory is either
two or four 512 MB DIMMs. Memory options are 512 MB, 1 GB, or 2 GB DIMMs.
There are a total of 28 DIMM sockets (two ports of 14). All 28 DIMM sockets can
be used to install DIMMs, with the exception of the 2 GB DIMM option. If 2 GB
DIMMs are installed, the total number of DIMM sockets that can be used is
limited to 20. A maximum of 40 GB of system memory is supported by populating
20 DIMM sockets each with a 2 GB DIMM.
DIMMs must be installed in matched pairs, since the DIMMs are two-way
interleaved. However, if memory is installed in matched fours (a matched pair in
each port), the system automatically detects this and will enable four-way
interleaving. With this, memory access is performed simultaneously from both
ports (two separate paths into the memory controller as shown in Figure 1-1 on
page 4), leading to improved memory performance.
See 3.1.2, “Memory” on page 41 for a further discussion of how memory is
implemented in the x450 and what you should consider before an x450
installation.
There are a number of advanced features implemented in the x450 memory
subsystem, collectively known as
Active Memory
:
Restriction:
The ability to hot-add or hot-replace memory is not available in
the x450.