Intel D865GSA Product Specification - Page 48

Fixed I/O Map

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Intel Desktop Board D865GSA Technical Product Specification 2.2 Fixed I/O Map Table 16. I/O Map Address (hex) Size Description 0000 - 00FF 256 bytes 0170 - 0177 01F0 - 01F7 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 0374 - 0377 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 03F8 - 03FF 04D0 - 04D1 LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 4 bytes 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 4 bytes 8 bytes 2 bytes 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes Used by the Desktop Board D865GSA. Refer to the ICH5 data sheet for dynamic addressing information. Secondary Parallel ATE IDE channel command block Primary Parallel ATE IDE channel command block LPT3 LPT2 COM4 COM2 Secondary Parallel ATA IDE channel control block LPT1 Intel 82865G GMCH Intel 82865G GMCH COM3 Diskette channel Primary Parallel ATA IDE channel control block COM1 Edge/level triggered PIC ECP port, LPTn base address + 400h PCI configuration address register Reset control register PCI configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only NOTE Some additional I/O addresses are not available due to ICH5 address aliassing. The ICH5 data sheet provides more information on address aliassing. For information about Obtaining the ICH5 data sheet Refer to Section 1.2 on page 15 48

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Intel Desktop Board D865GSA Technical Product Specification
48
2.2
Fixed I/O Map
Table 16. I/O Map
Address (hex)
Size
Description
0000 - 00FF
256 bytes
Used by the Desktop Board D865GSA.
Refer to the ICH5 data
sheet for dynamic addressing information.
0170 - 0177
8 bytes
Secondary Parallel ATE IDE channel command block
01F0 - 01F7
8 bytes
Primary Parallel ATE IDE channel command block
0228 - 022F
(Note 1)
8 bytes
LPT3
0278 - 027F
(Note 1)
8 bytes
LPT2
02E8 - 02EF
(Note 1)
8 bytes
COM4
02F8 - 02FF
(Note 1)
8 bytes
COM2
0374 - 0377
4 bytes
Secondary Parallel ATA IDE channel control block
0378 - 037F
8 bytes
LPT1
03B0 - 03BB
12 bytes
Intel 82865G GMCH
03C0 - 03DF
32 bytes
Intel 82865G GMCH
03E8 - 03EF
8 bytes
COM3
03F0 - 03F5
6 bytes
Diskette channel
03F4 - 03F7
4 bytes
Primary Parallel ATA IDE channel control block
03F8 - 03FF
8 bytes
COM1
04D0 - 04D1
2 bytes
Edge/level triggered PIC
LPTn + 400
8 bytes
ECP port, LPTn base address + 400h
0CF8 - 0CFB
(Note 2)
4 bytes
PCI configuration address register
0CF9
(Note 3)
1 byte
Reset control register
0CFC - 0CFF
4 bytes
PCI configuration data register
FFA0 - FFA7
8 bytes
Primary Parallel ATA IDE bus master registers
FFA8 - FFAF
8 bytes
Secondary Parallel ATA IDE bus master registers
Notes:
1.
Default, but can be changed to another address range
2.
Dword access only
3.
Byte access only
±
NOTE
Some additional I/O addresses are not available due to ICH5 address aliassing.
The
ICH5 data sheet provides more information on address aliassing.
For information about
Refer to
Obtaining the ICH5 data sheet
Section 1.2 on page 15