Intel DZ68ZV Product Guide for Intel Desktop Board DZ68ZV - Page 78

CPU Initialization PEI, DXE, SMM, PEI Phase Before MRC - overclock

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Intel Desktop Board DZ68ZV Product Guide POST Code 11 12 13 14 15 16 17, 18 19, 1A 1B, 1C 21 23 24 27 28 29 2A, 2B 31, 33, 34 41-43 44-46 47-4C 4D-4F 50-52 58, 59 5A, 5B 5F 60-6F E4 E7 E8 E9 EB Description PEI Phase Before MRC Set bootmode, GPIO init Early chipset register programming Basic PCH init, discrete device init LAN init Exit early platform init driver SMBUS driver init Entry/Exit to SMBUS execute read/write Entry/Exit to CK505 programming Entry/Exit to PEI overclock programming MEC Memory Detection MRC entry point Reading SPD from memory DIMMs Detecting presence of memory DIMMs Configuring memory Testing memory Exit MRC driver PEI After MRC Start/finish programming MTRR settings PEIMs/Recovery Recovery has initiate, load, valid CPU Initialization (PEI, DXE, SMM) Begin to end CPU PEI init Begin to end CPU SMM init/relocate bases CPU DXE phase begin to end CPU DXE SMM phase begin to end I/O Buses PCI enumeration, allocation, hot plug Resetting USB bus Resetting SATA bus and all devices Unrecoverable error, start with PIC Boot Device Selection (BDS) BDS driver entry Entered DXE phase Waiting for user input Checking password Entering BIOS setup Calling legacy option ROMs 78

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Intel Desktop Board DZ68ZV Product Guide
78
POST Code
Description
PEI Phase Before MRC
11
Set bootmode, GPIO init
12
Early chipset register programming
13
Basic PCH init, discrete device init
14
LAN init
15
Exit early platform init driver
16
SMBUS driver init
17, 18
Entry/Exit to SMBUS execute read/write
19, 1A
Entry/Exit to CK505 programming
1B, 1C
Entry/Exit to PEI overclock programming
MEC Memory Detection
21
MRC entry point
23
Reading SPD from memory DIMMs
24
Detecting presence of memory DIMMs
27
Configuring memory
28
Testing memory
29
Exit MRC driver
PEI After MRC
2A, 2B
Start/finish programming MTRR settings
PEIMs/Recovery
31, 33, 34
Recovery has initiate, load, valid
CPU Initialization (PEI, DXE, SMM)
41-43
Begin to end CPU PEI init
44-46
Begin to end CPU SMM init/relocate bases
47-4C
CPU DXE phase begin to end
4D-4F
CPU DXE SMM phase begin to end
I/O Buses
50-52
PCI enumeration, allocation, hot plug
58, 59
Resetting USB bus
5A, 5B
Resetting SATA bus and all devices
5F
Unrecoverable error, start with PIC
Boot Device Selection (BDS)
60-6F
BDS driver entry
E4
Entered DXE phase
E7
Waiting for user input
E8
Checking password
E9
Entering BIOS setup
EB
Calling legacy option ROMs