LG KM710 Service Manual - Page 22

3. HW Circuit Description 3.3.2 Block Description The OMAPV1030 E-GPRS multimedia device is based on an OMAP3.4 platform that integrates: - The MPU subsystem - The DSP subsystem - A system DMA - A traffic controller providing: - External memory interfaces with: - A slow interface (EMIFS) to ROM, SRAM, FLASH memories - A fast interface (EMIFF) to SDRAM memories - Layer 3 (L3) interconnect made of two OCP target ports (OCP-T1 and OCP-T2) and one OCP initiator port (OCP-I) - Layer 4 (L4) interconnect made of two DSP peripheral busses (private DSP TIPB and shared DSP TIPB) and two MPU peripheral busses (public MPU TIPB and private MPU TIPB) - Clock management - A set of processor peripherals: - Three 32-bit timers, a 16-bit Watchdog timer, and an interrupt handler for the MPU - Three 32-bit timers, a 16-bit Watchdog timer, and a 2nd-level interrupt handler for the DSP - Test and debug interfaces (JTAG, Window Tracer) - Trace capabilities: ETM9 and Ctools The other OMAPV1030 modules or subsystems are connected to the OMAP3.4 platform through the L3 and L4 interconnects. OMAPV1030 Top-Level Architecture Overview Copyright © 2008 LG Electronics. Inc. All right reserved. Only for training and service purposes - 23 - LGE Internal Use Only