Sony HCD-C990 Service Manual - Page 96

Sony HCD-C990 - Compact Audio And Video System Manual

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HCD-C770/C990 Pin No. Pin Name I/O 53 XSRQ I 54 HINT O 55 XS16 O 56 HA1 I 57 XPDI I/O 58 VDDS - 59, 60 HA0, HA2 I 61 VSS - 62, 63 HCS0, HCS1 I 64 VDD - 65 DASP I/O 66 to 69 MDB0 to MDB3 I/O 70 VSS - 71 MDB4 I/O 72 VDD5V - 73 to 75 MDB5 to MDB7 I/O 76 XMWR O 77 VDD - 78 XRAS O 79, 80 MA0, MA1 O 81 VSS - 82 to 87 MA2 to MA7 O 88 VDD - 89 MA8 O 90 VSS - 91 MA9 O 92 MNT1 O 93 MNT2 O 94 XMOE O 95 XCAS O 96, 97 MDB8, MDB9 I/O 98 VSS - 99 MDBA I/O 100 VDD - 101, 102 MDBB, MDBC I/O 103 VDD5V - 104 to 106 MDBD to MDBF I/O 107 GFS O 108 VSS - 109 APEO O 110 VDD - 111 DASYO O 112 GNDA5 - 113, 114 ASF1, AFS2 - 115 DASYI I Description DVD mode: Serial data request signal input from the DVD system processor SACD mode: Serial data request signal input from the DSD decoder Not used Not used Not used Not used Power supply terminal (+5V) (digital system) Not used Ground terminal (digital system) Not used Power supply terminal (+3.3V) (digital system) Not used Two-way data bus with the D-RAM Ground terminal (digital system) Two-way data bus with the D-RAM Power supply terminal (+5V) Two-way data bus with the D-RAM Write enable signal output to the D-RAM Power supply terminal (+3.3V) (digital system) Row address strobe signal output to the D-RAM Address signal output to the D-RAM Ground terminal (digital system) Address signal output to the D-RAM Power supply terminal (+3.3V) (digital system) Address signal output to the D-RAM Ground terminal (digital system) Address signal output to the D-RAM EEPROM ready signal output to the mechanism controller Operation clock signal output for PSP physical disc mark detection to DSD decoder Output enable signal output to the D-RAM Column address strobe signal output to the D-RAM Two-way data bus with the D-RAM Ground terminal (digital system) Two-way data bus with the D-RAM Power supply terminal (+3.3V) (digital system) Two-way data bus with the D-RAM Power supply terminal (+5V) Two-way data bus with the D-RAM Guard frame sync signal output to the mechanism controller Ground terminal (digital system) Absolute phase error signal output Power supply terminal (+3.3V) (digital system) RF binary signal output Ground terminal (analog system) Filter connected terminal for selection the constant asymmetry compensation Analog signal input after integrated from the RF binary signal 96

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96
HCD-C770/C990
Pin No.
Pin Name
I/O
Description
53
XSRQ
I
DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
—
Power supply terminal (+5V)
(digital system)
59, 60
HA0, HA2
I
Not used
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply terminal (+3.3V)
(digital system)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply terminal (+3.3V)
(digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply terminal (+3.3V)
(digital system)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground terminal (digital system)
91
MA9
O
Address signal output to the D-RAM
92
MNT1
O
EEPROM ready signal output to the mechanism controller
93
MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply terminal (+3.3V)
(digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the mechanism controller
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V)
(digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal