Sony HCD-C990 Service Manual - Page 99

Dvd Board, Ic801, Cxd2752r Dsd Decoder

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HCD-C770/C990 • DVD BOARD IC801 CXD2752R (DSD DECODER) Pin No. Pin Name I/O 1 VSCA0 - 2 XMSLAT I 3 MSCK I 4 MSDATI I 5 VDCA0 - 6 MSDATO O 7 MSREADY O 8 XMSDOE O 9 XRST I 10 SMUTE I 11 MCKI I 12 VSIOA0 - 13 EXCKO1 O 14 EXCKO2 O 15 LRCK O 16 F75HZ O 17 VDIOA0 - 18 to 25 MNT0 to MNT7 O 26 TCK I 27 TDI I 28 VSCA1 - 29 TDO O 30 TMS I 31 TRST I 32 to 34 TEST1 to TEST3 I 35 VDCA1 - 36 UBIT O 37 XBIT O 38 to 41 SUPDT0 to O SUPDT3 42 VSIOA1 - 43, 44 SUPDT4, SUPDT5 O 45 VDIOA1 - 46, 47 SUPDT6, SUPDT7 O 48 SUPEN O 49 VSCA2 - 50 NC O 51, 52 TEST4, TEST5 I 53 NC O 54 VDCA2 - 55, 56 NC O 57 BCKASL I 58 VSDSD0 - 59 BCKAI I 60 BCKAO O Description Ground terminal (for core) Serial data latch pulse signal input from the mechanism controller Serial data transfer clock signal input from the mechanism controller Serial data input from the mechanism controller Power supply terminal (+2.5V) (for core) Serial data output to the mechanism controller Ready signal output to the mechanism controller "L": ready Serial data output enable signal output terminal Not used Reset signal input from the mechanism controller "L": reset Soft muting on/off control signal input from the mechanism controller "H": muting on Master clock signal (33.8688 MHz) input Ground terminal (for I/O) Master clock signal (33.8688 MHz) output to the digital audio processor External clock 2 signal output terminal Not used L/R sampling clock signal (44.1kHz) output terminal Not used Not used Power supply terminal (+3.3V) (for I/O) Monitor signal output terminal Not used Clock signal input from the DVD system processor Serial data input from the DVD system processor Ground terminal (for core) Serial data output to the DVD system processor MS signal input from the DVD system processor Reset signal input from the DVD system processor "L": reset Input terminal for the test (normally: fixed at "L") Power supply terminal (+2.5V) (for core) Not used Not used Supplementary data output terminal Not used Ground terminal (for I/O) Supplementary data output terminal Not used Power supply terminal (+3.3V) (for I/O) Supplementary data output terminal Not used Supplementary data enable signal output terminal Not used Ground terminal (for core) Not used Input terminal for the test (normally: fixed at "L") Not used Power supply terminal (+2.5V) (for core) Not used Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output "L": input (slave), "H": output (master) Fixed at "H" in this set Ground terminal (for DSD data output) Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used 99

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99
HCD-C770/C990
•
DVD BOARD
IC801
CXD2752R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSCA0
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the mechanism controller
3
MSCK
I
Serial data transfer clock signal input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller
“L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal
Not used
9
XRST
I
Reset signal input from the mechanism controller
“L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller
“H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input
12
VSIOA0
—
Ground terminal (for I/O)
13
EXCKO1
O
Master clock signal (33.8688 MHz) output to the digital audio processor
14
EXCKO2
O
External clock 2 signal output terminal
Not used
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal
Not used
16
F75HZ
O
Not used
17
VDIOA0
—
Power supply terminal (+3.3V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output terminal
Not used
26
TCK
I
Clock signal input from the DVD system processor
27
TDI
I
Serial data input from the DVD system processor
28
VSCA1
—
Ground terminal (for core)
29
TDO
O
Serial data output to the DVD system processor
30
TMS
I
MS signal input from the DVD system processor
31
TRST
I
Reset signal input from the DVD system processor
“L”: reset
32 to 34
TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDCA1
—
Power supply terminal (+2.5V) (for core)
36
UBIT
O
Not used
37
XBIT
O
Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal
Not used
42
VSIOA1
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal
Not used
45
VDIOA1
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal
Not used
48
SUPEN
O
Supplementary data enable signal output terminal
Not used
49
VSCA2
—
Ground terminal (for core)
50
NC
O
Not used
51, 52
TEST4, TEST5
I
Input terminal for the test (normally: fixed at “L”)
53
NC
O
Not used
54
VDCA2
—
Power supply terminal (+2.5V) (for core)
55, 56
NC
O
Not used
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master)
Fixed at “H” in this set
58
VSDSD0
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output
Not used
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output
Not used